1 / 20

Total Dose and SEE of Metal-To-Metal Antifuse FPGA

Total Dose and SEE of Metal-To-Metal Antifuse FPGA. J. Wang, B. Cronquist, J. McCollum, F. Hawley, D. Yu, R. Chan and R. Balasubramanian Actel Corporation, Sunnyvale, California R. Katz NASA/GSFC, Greenbelt, Maryland I. Kleyner Orbital Science Corporation, Germantown, Maryland. Outline.

anika
Download Presentation

Total Dose and SEE of Metal-To-Metal Antifuse FPGA

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Total Dose and SEE of Metal-To-Metal Antifuse FPGA J. Wang, B. Cronquist, J. McCollum, F. Hawley, D. Yu, R. Chan and R. Balasubramanian Actel Corporation, Sunnyvale, California R. Katz NASA/GSFC, Greenbelt, Maryland I. Kleyner Orbital Science Corporation, Germantown, Maryland

  2. Outline 1. Introduction to M2M antifuse FPGA 2. Total Ionizing Dose 3. Single Event Effects • SEU • SEL • SEDR 4. Summary

  3. RT54SX • 16k, 32k, 72k gate antifuse FPGA • 0.6mm (3.3/5.0V), 0.25mm (2.5/3.3/5.0V) CMOS technology • Commercial foundry

  4. Sea-of-Module Architecture

  5. Sea-of-Module Architecture

  6. Combinatorial Cell Register Cell PSETB D0 DIN S1 S0 D1 Y Y D Q D2 DC IN D3 Sa Sb HCLK CLKA, CLKB DB CKS CKP CLRB A0 B0 A1 B1 Basic Logic Modules

  7. Metal 3 Metal-to-Metal Antifuse Metal 2 Via Metal 1 Contact Silicon M2M Antifuse

  8. SX Pin-to-Pin Performance • Fast, Flexible Array Logic and Routing • Fast pin-to-pin timing Input TPD 0.6ns TIRD1 0.3ns Array C-Cells TFC 0.3ns TINYH/INYL 1.5ns TPD 0.6ns TFC 0.3ns TPD 0.6ns Output TRD1 0.3ns TDLH/DHL 1.6ns Total Pin-to-Pin Timing, 32-bit Decode 6.1ns Numbers shown for A54SX16-3, worst case commercial conditions

  9. RTSX TID • 0.6mm • Tolerance limited by static ICC • 100krad(Si) • 0.25mm • Tolerance limited by static ICC • Shallow trench isolation • 65krad(Si) before improvement, 250krad(Si) after improvement

  10. 0.6mm RTSX TID

  11. 0.6mm RTSX TID (Proton)

  12. 0.25mm RTSX TID

  13. 0.6mm RTSX SEU

  14. User Level SEU Hardening

  15. 0.25mm RTSX SEU

  16. IN FF 1 Voter OUT FF 2 FF 3 CLK SEU-Hard TMR Flip-Flop

  17. Heavy Ion N+ N+ Single Strike Double Upset in SEU Hard FF Simulated by using Space Rad 4.0, Multiple-Bit Upset module Active Junction in FF2 Active Junction in FF1

  18. Single Event Latchup • RT54SX is latchup immune, i.e., LETth >120MeV-cm2/mg

  19. Heavy Ion Top Metal VCC Dielectric Bottom Metal Single Event Dielectric Rupture • Antifuse structure 1: Both 0.6mm and 0.25mm are immune to SEDR. • Antifuse structure 2: 0.6mm • Original structure has LETth=40MeV-cm2/mg at VCC=3.3V. • New recipe is immune (no rupture at right angle incidence, LET=60MeV-cm2/mg, VCC>3.6V). E-fieldM2M ~3.3V/700A ~0.5MV/cm E-fieldONO ~5V/100A ~5MV/cm

  20. SUMMARY • TID • RTSX has good tolerance, 50k-100krad(Si). • Smaller geometry shows potential for higher tolerance. • SEU • 0.6mm RTSX shows better tolerance than ACT2, ACT3 (ONO). • FF LETth: SX=11, ACT2/3=4 • CC LETth: SX>40, ACT2/3=20 • 0.25mm RTSX have hardened FF option. • SEL • RT/RHSX are immune. • SEDR • RT/RHSX are immune.

More Related