1 / 5

The LIGO Timing System

The LIGO Timing System. LSC Seminar, May 23, 2003 Daniel Sigg. Design/Requirements. 10 m s absolute calibration of incoming GW waves 1 m s clock accuracy Use a GPS master clock in all buildings Use IRIG-B slaves in each VME crate (UTC – GPS leap seconds)

anjelita-ortiz
Download Presentation

The LIGO Timing System

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. The LIGO Timing System LSC Seminar, May 23, 2003 Daniel Sigg

  2. Design/Requirements • 10ms absolute calibration of incoming GW waves • 1ms clock accuracy • Use a GPS master clock in all buildings • Use IRIG-B slaves in each VME crate(UTC – GPS leap seconds) • Synchronize the ADC modules using a hardware clock signal • Use a NTP server for the control room workstations LIGO I

  3. Implementation • GPS master in DAQ controller for timestamp • 1 second mark • Second GPS master with a 224Hz quartz oscillator • Feeds clock driver module (1pps and 222Hz) • Ramp signal at 1pps, IRIG-B slave signal • Trigger signals for ADC modules • Data collection: reflective memory loop • 1/16s buffers, 1/2s ring buffer • Collected and time stamped by DAQ controller (1s) • 2s ring buffer to frame builder (1/16s buffers) • 16s frame files • Excitations are written to refl. mem. (using GPS time) • Photon Calibrator LIGO I

  4. Front-End / T020196Rolf Bork, Dale Ouimette • Initialization/Auto-resync • Diagnostics • GPS Ramp => absolute • CPU meter overload => lost IO cycles • Polling ADC/Clock ready bitADC ready at the same time as clock?=> late ADC samples • Resync counterADC ready at end of processing?=> missed ADC samples • Cycle countEveryone on the same sample count?=> inter-crate synchronization • Processing Time @ 16kHz • LSC: 46ms, LVEA LOS: 56ms,ETM: 45ms, MC2: 27ms LIGO I

  5. Timing Diagram LIGO I

More Related