Power vs. Scaling as (Over-)Constrained Optimization

1. Power vs. Scalingas (Over-)Constrained Optimization Andrew B. Kahng Design ITWG UC San Diego CSE and ECE Depts. abk@ucsd.edu

2. Outline • Modeling and Scaling • Constraints • The Power Management Challenge • (= evidence of overconstraints) • How can we attack this? • (= what constraints can be relaxed?)

3. Modeling and Scaling • System content (MPU HP, MPU CP, SOC-LP), chip sizes, densities • Logic, memory switching activity and power models • Dynamic power: A*f*C * V2 • A*f = switching probability * clock frequency = effective switching frequency • Scales with device t (e.g., 17% per year for HP device)  1.4x per node • C = total switched capacitance • Device • Cox * W * L • EOT scaling  Cox1.4x per node • W 1.4x, L 0.7x cancel out  total device cap 1.4x per node • Interconnect (each layer 50% area coverage, no coupling cap) • ~ +1 layer per node • V = supply voltage (0.85x per node) • V2 scales by 0.7x per node (roughly cancels A*f scaling) • Static power • Total device width 1.4x / node, Ioff per unit width 3-5x / node  6x / node • All devices assumed to leak continuously • Static overtakes Dynamic during 90nm node (purely HP devices)

4. Constraints • System Drivers constrained by modeled die size, content, density • MPU • Logic content, memory content (#transistors) each double per node • SOC-LP PDA (STRJ) • Consumes 0.1W peak power, 2.1mW standby power • Processing power (GOps) increases 4x faster than clock frequency  logic content increases rapidly • Battery technology: 120 Wh/Kg in 2001  400 Wh/Kg in 2010 • PIDS • High-performance device CV/I must improve 17% per year • Low standby power device Ioff = 1pA/um • Assembly and Packaging • Max power (W) for HP MPU: +2x over entire roadmap (cost constraints) • 130W in 2001  288W in 2016 • Other key parameters (e.g., junction temps) roughly flat • Others (largely unaddressed) • Psychophysics (law of logarithmic utility in consumer products) • Current delivery and reliability: P/G network cross-sections vs. currents • Signal integrity (IR drop, L dI/dt noise) • Modeling (IR drop, thermal variability impact on timing correctness)

5. The Power Management Challenge • Challenges = evidence of overconstraints • “Power Management Gap” • (Estimated_System_Power – Power_Budget) / Power_Budget • MPU HP: 823W at 65nm node, 4036W at 22nm node •  ~ 15X power management gap at end of Roadmap • SOC LP: Standby power management gap reaches 800X in 2016 • Who/What is being challenged? • Test (burn-in, ATE (power, pincount)) • Packaging (power delivery, power removal) • PIDS (flavors (HP, LOP, LSTP), multi-(Vdd, Vt, tox), costs-benefits) • Interconnect (power delivery while maintaining signaling bandwidths) • Design (management of interfaces to architecture/OS/application, and of costs of technology-based solutions) • ESH (not just manufacturing, but devices themselves) • Ultimately, the ability to extract value from continuation of the process roadmap •  Cost and ROI considerations!

6. How Can We Attack This? • Must escape the overconstrained optimization regime • Change the problem? and/or Relax constraints? • Changing the problem • Architecture and content assumptions are wrong? • Or, is the problem really harder? • Power-optimistic LSTP roadmap • System-level power optimization is really difficult • Relaxing constraints • Rate of scaling? (analog, low-power devices = non-scaled devices?) • Fuel cells? 10x improvement in W-hours/Kg • Package cost constraints (eliminate the package?) • Cooling technologies (closed-loop, thermoelectric, …) • Device and dynamic flexibility • Multi-everything in core • Substrate biasing • Dynamic voltage, frequency scaling • Architectures (parallelism, uArch tweaks), OS (f, V scaling; gating) • Spatial embedding: X Architecture, stacking, … • Bottom line • Key DOFs both inside / outside traditional ITRS scope • Constrained optimization mindset  place focused bets for R&D