CS1104 – Computer Organization http://www.comp.nus.edu.sg/~cs1104

1. CS1104 – Computer Organizationhttp://www.comp.nus.edu.sg/~cs1104 Aaron Tan Tuck Choy School of Computing National University of Singapore

2. Lecture 14: Introduction to Algorithmic State Machines (ASM) • Large Digital Systems • Top-Down Approach • Controller and Data Processor • Flowcharts • ASM Charts • Components of ASM Charts • ASM Charts: An Example • Register Operations • Timing in ASM Charts Lecture 14: Introduction to Algorithmic State Machines (ASM)

3. Lecture 14: Introduction to Algorithmic State Machines (ASM) • ASM Charts => Digital System • ASM Charts => Controller • ASM Charts => Architecture/Data Processor • Implementing the Controller • With JK Flip-flops • Decoder + D flip-flops • One Flip-flop per State • Multiplexers • PLA/ROM Lecture 14: Introduction to Algorithmic State Machines (ASM)

4. Large Digital Systems • In both combinational and sequential circuit design: • small circuits via gate-level design (truth tables, K maps, etc) • large circuits via block-level design (MSI components, etc.) • However, larger digital systems need more abstract and systematic design techniques. • One such systematic design method has the following characteristics: • top-down approach • separation of controller from controlled hardware • develop an overall architecture (at block levels) before proceeding into the details of hardware. Large Digital Systems

5. Top-Down Approach • Top-down approach is immensely important for large complex system (whether hardware, software, or manual systems). • Emphasis on macroscopic view, starting from original problem and gradually refine it towards solution. • Steps for a top-down design procedure: • Specify the problem clearly (at global/top level without unnecessary details). • Break the problem into smaller sub-problems. • Repeat the process until subproblems are small enough to be solved directly (implementable). Top-Down Approach

6. Pass CS1103 Do Tutorials Pass Tests Pass Exam Ask questions Practice Revise Sleep well Top-Down Approach • Corresponds to goal-directed approach. • State goal, then find sub-goals to solve main goal. • Repeat until sub-goals are directly solvable. Top-Down Approach

7. Controller & Data Processor • Digital systems are typically processors of information. • They store data through flip-flops, registers and memory, and process them using combinational circuits like adders, multipliers, etc. • These processing may pass through complicated sequences. Controller & Data Processor

8. Status condition Commands Data Processor (Architecture) Control unit (Controller) External command Input data Output data Controller & Data Processor • A digital system consists of two components • A control algorithm (controller) and • An architecture (data processor) Controller & Data Processor

9. Controller & Data Processor • Separation of the controller operations from the data processing operations • Control operations give commands that direct the data processing operations to accomplish the desired tasks. • Data processing operations manupulates the data according to requirements. • A mechanical analogy: Automobile. • Car (data processor): transports people from one location to another. • Driver (controller): gives instructions to car to achieve objective. Controller & Data Processor

10. Flowcharts • Flowcharts: a tool for precise description of algorithms/procedures. • Specify tasks to perform and their sequencing. • Main symbols: • Operation box: contains tasks/operations to perform. • Decision box: alternative actions based on decisions to be taken. • Arrows: indicate appropriate sequencing. Flowcharts

11. Sub-task or operation to perform Flowcharts • An operation box is rectangular in shape, and is used to specify one or more subtasks to be performed. It has at most one entry point and one exit point. Flowcharts

12. choice option A option B option C Flowcharts • A decision box is diamond-shaped. It has one entry point and multiple (but mutually exclusive) exit points. Flowcharts

13. Drink soup Main course Eat dessert Flowcharts • Sequential flow: simplest type of sequencing; tasks are done in sequential order. • An example: Eating a 3-course Western meal. • Boxes are connected by lines with arrows. Lines without arrows are sometimes used. In the absence of arrows, the default flow direction is top-to-bottom and left-to-right. Flowcharts

14. Flowcharts • Iteration: some tasks/operations may be repeatedly/iteratively done. • This is achieved through the loop-back in the flowchart. • Decision box is used to determine when to terminate the loop. Flowcharts

15. Drink soup Main course no enough? yes Eat dessert Flowcharts • An example: Eating a Western meal in oriental style. Flowcharts

16. yes nice colour & style? yes no affordable? no made in Europe? yes test out no poor fitting? accep-table insulting BF’s opinion? encouraging reject get BF to buy Flowcharts • Flowcharts can be used to implement complex decisions. Flowcharts

17. ASM Charts • Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems. • Major differences from flowcharts are: • uses 3 types of boxes: state box (similar to operation box), decision box and conditional box • contains exact (or precise) timing information; flowcharts impose a relative timing order for the operations. • From the ASM chart it is possible to obtain • the control • the architecture (data processor) ASM Charts

18. binary code state one or more operations Components of ASM Charts • The state box is rectangular in shape. It has at most one entry point and one exit point and is used to specify one or more operations which could be simultaneously completed in one clock cycle. Components of ASM Charts

19. deciding factors deciding factors Components of ASM Charts • The decision box is diamond in shape. It has one entry point but multiple exit points and is used to specify a number of alternative paths that can be followed. Components of ASM Charts

20. conditional operations Components of ASM Charts • The conditional box is represented by a rectangle with rounded corners. It always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box. Components of ASM Charts

21. T0 Initial state 0 S 1 A  0 F  0 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 T2 1 F  1 ASM Charts: An Example • An example: A is a register; Ai stands for ith bit of the A register. A = A4A3A2A1 E and F are single-bit flip-flops. ASM Charts: An Example

22. Register Operations • Registers are present in the data processor for storing and processing data. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers. • The register operations are specified in either the state and/or conditional boxes, and are written in the form: destination registerfunction(other registers) where the LHS contains a destination register (or part of one) and the RHS is some function over one or more of the available registers. Register Operations

23. Register Operations • Examples of register operations: A  B Transfer contents of register B into register A. A  0 Clear register A. A  A  1 Decrement register A by 1. Register Operations

24. Timing in ASM Charts • Precise timing is implicitly present in ASM charts. • Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle. • A group of boxes which occur within a single clock cycle is called an ASM block. Timing in ASM Charts

25. T0 Initial state 0 S 1 A  0 F  0 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 T2 1 F  1 Timing in ASM Charts 3 ASM blocks Timing in ASM Charts

26. Timing in ASM Charts • Operations of ASM can be illustrated through a timing diagram. • Two factors which must be considered are • operations in an ASM block occur at the same time in one clock cycle • decision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block) Timing in ASM Charts

27. A0 F0 AA+1 E0 AA+1 E1 AA+1 E0 F1 Operations AA+1 E0 AA+1 E1 AA+1 E0 AA+1 E1 A = A4A3A2A1 Timing in ASM Charts Timing in ASM Charts

28. T0 Initial state 0 S 1 A0 F0 AA+1 E0 AA+1 E1 A  0 F  0 Operations AA+1 E0 AA+1 E1 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 AA+1 E0 F1 Operations T2 1 F  1 AA+1 E0 AA+1 E1 Timing in ASM Charts A = A4A3A2A1 Timing in ASM Charts

29. ASM Chart => Digital System • ASM chart describes a digital system. From ASM chart, we may obtain: • Controller logic (via State Table/Diagram) • Architecture/Data Processor • Design of controller is determined from the decision boxes and the required state transitions. • Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes. ASM Chart => Digital System

30. ASM Chart => Controller • Procedure: • Step 1: Identify all states and assign suitable codes. • Step 2: Draw state diagram. • Step 3: Formulate state table using State from state boxes Inputs from decision boxes Outputs from operations of state/conditional boxes. • Step 4: Obtain state/output equations and draw circuit. ASM Chart => Controller

31. T0 Assign codes to states: T0 = 00 T1 = 01 T2 = 11 T2 T0 T1 Initial state 0 S 1 A  0 F  0 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 Inputs from conditions in decision boxes. Outputs = present state of controller. T2 1 F  1 ASM Chart => Controller ASM Chart => Controller

32. ASM Chart => Architecture/Data Processor • Architecture is more difficult to design than controller. • Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine: • What registers to use • How they can be connected • What operations to support • How these operations are activated. • Guidelines: • always use high-level units • simplest architecture possible. ASM Chart => Architecture/Data Processor

33. ASM Chart => Architecture/Data Processor • Various operations are: • Counter incremented (A  A + 1) when state = T1. • Counter cleared (A  0) when state = T0 and S = 1. • E is set (E  1) when state = T1 and A2 = 1. • E is cleared (E  0) when state = T1 and A2 = 0. • F is set (F  1) when state = T2. • Deduce: • One 4-bit register A (e.g.: 4-bit synchronous counter with clear/increment). • Two flip-flops needed for E and F (e.g.: JK flip-flops). ASM Chart => Architecture/Data Processor

34. S T0 start A3 Controller T1 Clk A2 T2 Q J E K Q J F K A4 A3 A2 A1 count 4-bit syn. counter A CP clear clock ASM Chart => Architecture/Data Processor • (A  A + 1) when state = T1. • (A  0) when state = T0 and S = 1. • (E  1) when state = T1 and A2 = 1. ASM Chart => Architecture/Data Processor

35. Implementing the Controller • Once the state table is obtained, the controller can be implemented using one of these techniques. • 1. Traditional method: With JK flip-flops. • design done at gate level. • suitable for small controllers. • procedure: prepare state table, use K-maps to obtain next-state/output functions. • 2. Decoder + D flip-flops • suitable for moderately large controllers. • procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection. Implementing the Controller

36. Implementing the Controller • 3. Multiplexers • a more structured approach to implement controller. • suitable for moderately large controllers. • three level structure: • first level consists of multiplexers that determine the next state of the register; • second level is a register that holds the present state; • third level has a decoder to provide separate output for each controller state. Implementing the Controller

37. Implementing the Controller • 4. One flip-flop per state • also known as One-Hot Spot Method of ASM synthesis. • procedure: allocate one flip-flop per state; from state table, determine the formulae to set each flip-flop; must ensure that controller is properly initialised. • 5. PLA/ROM • highly regular approach. • ROM approach uses a very simple table lookup technique but suffers from large number of don’t care states. • PLA can handle don’t care states well but design method is still at gate-level. Implementing the Controller

38. Implementing Controller:With JK Flip-flops • State table obtained from ASM chart: • Corresponding state table using JK flip-flops: Implementing Controller: With JK Flip-flops

39. G1 ? D Q T0 2x4 decoder T1 G0 D ? unused Q T2 clock Implementing Controller:Decoder + D Flip-flops • The flip-flop input functions can be obtained directly from the state table by inspection. • This is because for the D flip-flops, the next state = flip-flop D input. • Decoder is then used to provide signals to represent different states. Implementing Controller: Decoder + D Flip-flops

40. Implementing Controller:Decoder + D Flip-flops • Given the state table: • We can directly determine the inputs of the D flip-flops for G1 and G0. DG1 = T1.A2.A3 DG0 = T0.S + T1 Implementing Controller: Decoder + D Flip-flops

41. A2 G1 D Q A3 T0 2x4 decoder T1 G0 D unused Q S T2 clock Implementing Controller:Decoder + D Flip-flops • Flip-flop input functions: DG1 = T1.A2.A3 DG0 = T0.S + T1 • Circuit: Implementing Controller: Decoder + D Flip-flops

42. ? T0 ? T1 D Q : : D Q clock Implementing Controller:One Flip-flop per State • Require n flip-flops for n states; each flip-flop represents one state. (Other methods: n flip-flops for up to 2n states.) Implementing Controller: One Flip-flop per State

43. Implementing Controller:One Flip-flop per State • Formulae for next state can be obtained directly from state table: • 1. If there is only one line going into the state, then formula = input condition ANDed with the previous state. • 2. If there are more than one line, then formula = Ored of all the conditions found in (1). Implementing Controller: One Flip-flop per State

44. S=0 A2=0 S=1 T0 T1 A2=1, A3=0 A2=1, A3=1 T2 Implementing Controller:One Flip-flop per State • State table: • State diagram: • Flip-flop input functions: DT0 = T2 + S'.T0 DT1 = S.T0 + A2'.T1 + A2.A3'.T1 = S.T0 + (A2.A3)'.T1 DT2 = A2.A3.T1 Implementing Controller: One Flip-flop per State

45. preset T0 D D D Q Q Q S T1 A2 A3 T2 clock clear Implementing Controller:One Flip-flop per State • Circuit diagram below. To initialise to state T0, set flip-flop of T0 to 1 and clear the rest to zero. DT0 = T2 + S'.T0 DT1 = S.T0 + (A2.A3)'.T1 DT2 = A2.A3.T1 Implementing Controller: One Flip-flop per State

46. D D D Q Q Q S Q' T0 T1 A2 A3 T2 clock clear Implementing Controller:One Flip-flop per State • Alternative: Use Q' output for T0, and input function for T0 is complemented. To initialise, clear all flip-flops to zero. DT0 = (T2 + S'.T0)' DT1 = S.T0 + (A2.A3)'.T1 DT2 = A2.A3.T1 Implementing Controller: One Flip-flop per State

47. Implementing Controller:Multiplexers • Purpose of multiplexer is to produce an input to its corresponding flip-flop equals to the value of the next state. • The inputs of multiplexers are determined from the decision boxes and state transitions in the ASM chart. Implementing Controller: Multiplexers

48. Implementing Controller:Multiplexers • Example 1: Given the state table. • Reformat the state table. Implementing Controller: Multiplexers

49. Implementing Controller:Multiplexers • Obtain multiplexer inputs: Implementing Controller: Multiplexers

50. D D Q Q 0 0 1 2 3 A2 A3 G1 MUX1 0 S1 S0 T0 2x4 decoder T1 S1 S0 S T2 0 1 2 3 G0 1 MUX0 0 clock Determine next state of register Hold present state Implementing Controller:Multiplexers • Draw circuit: Implementing Controller: Multiplexers