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CS 230: Computer Organization and Assembly Language

CS 230: Computer Organization and Assembly Language. Aviral Shrivastava. Department of Computer Science and Engineering School of Computing and Informatics Arizona State University. Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB. Announcements.

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CS 230: Computer Organization and Assembly Language

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  1. CS 230: Computer Organization and Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB

  2. Announcements • Project 4 • MIPS Simulator • Due Nov 10, 2009 • Alternate Project • Quiz 5 • Thursday, Nov 19, 2009 • Pipelining • Finals • Tuesday, Dec 08, 2009 • Please come on time (You’ll need all the time) • Open book, notes, and internet • No communication with any other human

  3. Benefits of Pipelining Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Dec/Reg • Exec Mem • Wr Ifetch Dec/Reg • Exec Mem • Wr Ifetch Dec/Reg • Exec Mem • Wr pipelined Ifetch Dec/Reg • Exec Mem • Wr • Pipeline latches: pass the status and result of the current instruction to next stage • Comparison: Clock Single- cycle inst. Dec/Reg • Exec Ifetch Mem Ifetch sw lw

  4. Passing control w/pipe registers strip off signals for execution phase strip off signals for WB memory phase n strip off signals for o M Control WB i t write-back phase c Genera- u r tion t s EX M WB n I RegDst Branch MemtoReg ALUOp MemRead RegWrite ALUSrc MemWrite IF/ID ID/EX EX/MEM MEM/WB • Analogy: send instruction with car on assembly line • “Install Corinthian leather interior on car 6 @ stage 3”

  5. The hazards of pipelining • Pipeline hazards prevent next instruction from executing during designated clock cycle • There are 3 classes of hazards: • Structural Hazards: • Arise from resource conflicts • HW cannot support all possible combinations of instructions • Data Hazards: • Occur when given instruction depends on data from an instruction ahead of it in pipeline • Control Hazards: • Result from branch, other instructions that change flow of program (i.e. change PC)

  6. Structural Hazard ALU ALU ALU ALU ALU Mem Mem Mem Mem Mem Reg Reg Reg Reg Reg DM DM DM DM DM Reg Reg Reg Reg Reg Load Instruction 1 Instruction 2 Instruction 3 Instruction 4 What’s the problem here? Time CSE 420: Computer Architecture

  7. Structural hazards • A way to avoid structural hazards is to duplicate resources • i.e.: An ALU to perform an arithmetic operation and an adder to increment PC • If not all possible combinations of instructions can be executed, structural hazards occur • Most common instances of structural hazards: • When a functional unit not fully pipelined • When some resource not duplicated enough CSE 420: Computer Architecture

  8. How is it resolved? ALU ALU ALU ALU Mem Mem Mem Mem Reg Reg Reg Reg DM DM DM DM Reg Reg Reg Reg Bubble Bubble Bubble Bubble Bubble Load Instruction 1 Instruction 2 Stall Instruction 3 Pipeline generally stalled by inserting a “bubble” or NOP Time CSE 420: Computer Architecture

  9. Or alternatively… Clock Number • LOAD instruction “steals” an instruction fetch cycle which will cause the pipeline to stall. • Thus, no instruction completes on clock cycle 8 CSE 420: Computer Architecture

  10. Example: Dual-port vs. Single-port • Machine A: Dual ported memory (“Harvard Architecture”) • Machine B: Single ported memory, but its pipelined implementation has a 1.05 times faster clock rate • Ideal CPI = 1 for both • Loads are 40% of instructions executed SpeedUpA = Pipeline Depth/(1 + 0) x (clockunpipe/clockpipe) = Pipeline Depth SpeedUpB = Pipeline Depth/(1 + 0.4 x 1) x (clockunpipe/(clockunpipe / 1.05) = (Pipeline Depth/1.4) x 1.05 = 0.75 x Pipeline Depth SpeedUpA / SpeedUpB = Pipeline Depth/(0.75 x Pipeline Depth) = 1.33 • Machine A is 1.33 times faster CSE 420: Computer Architecture

  11. Illustrating a data hazard ALU ALU ALU ALU Mem Mem Reg Reg DM DM Reg Reg ADD R1, R2, R3 SUB R4, R1, R5 Mem Reg DM AND R6, R1, R7 Mem Reg OR R8, R1, R9 Mem Reg XOR R10, R1, R11 Time ADD instruction causes a hazard in next 3 instructions b/c register not written until after those 3 read it.

  12. One Way to “Fix” a Data Hazard DM DM DM Reg Reg Reg Reg Reg Reg stall IM IM IM ALU ALU ALU stall sub $4,$1,$5 and $6,$7,$1 Fix data hazard by waiting – stall – but impacts CPI add $1, I n s t r. O r d e r

  13. One Way to “Fix” a Data Hazard DM DM DM Reg Reg Reg Reg Reg Reg stall IM IM IM ALU ALU ALU stall sub $4,$1,$5 and $6,$7,$1 Fix data hazard by waiting – stall – but impacts CPI add $1, I n s t r. O r d e r

  14. Another Way to “Fix” a Data Hazard DM DM DM DM DM Reg Reg Reg Reg Reg Reg Reg Reg Reg Reg IM IM IM IM IM ALU ALU ALU ALU ALU Fix data hazards by forwarding results as soon as they are available to where they are needed add $1, I n s t r. O r d e r sub $4,$1,$5 and $6,$7,$1 or $8,$1,$1 sw $4,4($1)

  15. Data Forwarding (aka Bypassing) • Take the result from the earliest point that it exists in any of the pipeline state registers and forward it to the functional units (e.g., the ALU) that need it that cycle • For ALU functional unit: the inputs can come from any pipeline register rather than just from ID/EX by • adding multiplexors to the inputs of the ALU • connecting the Rd write data in EX/MEM or MEM/WB to either (or both) of the EX’s stage Rs and Rt ALU mux inputs • adding the proper control hardware to control the new muxes • Other functional units may need similar forwarding logic (e.g., the DM) • With forwarding can achieve a CPI of 1 even in the presence of data dependencies

  16. When can we forward? ALU ALU ALU ALU Mem Mem Reg Reg DM DM Reg Reg ADD R1, R2, R3 SUB gets info. from EX/MEM pipe register AND gets info. from MEM/WB pipe register OR gets info. by forwarding from register file SUB R4, R1, R5 Mem Reg DM AND R6, R1, R7 Mem Reg OR R8, R1, R9 Mem Reg XOR R10, R1, R11 Rule of thumb: If line goes “forward” you can do forwarding. If its drawn backward, it’s physically impossible. Time

  17. Datapath with Forwarding Hardware ID/EX EX/MEM Control IF/ID Add MEM/WB Branch Add 4 Shift left 2 Read Addr 1 Instruction Memory Data Memory Register File Read Data 1 Read Addr 2 Read Address PC Read Data Address Write Addr ALU Read Data 2 Write Data Write Data ALU cntrl 16 32 Sign Extend EX/MEM.RegisterRd ID/EX.RegisterRt Forward Unit MEM/WB.RegisterRd ID/EX.RegisterRs PCSrc ForwardA ForwardB

  18. Data Forwarding Control Conditions • EX/MEM hazard: if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 Forwards the result from the previous instr. to either input of the ALU 2. MEM/WB hazard: if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01 Forwards the result from the second previous instr. to either input of the ALU

  19. Yet Another Complication! DM DM DM Reg Reg Reg Reg Reg Reg IM IM IM ALU ALU ALU • Another potential data hazard can occur when there is a conflict between the result of the WB stage instruction and the MEM stage instruction – which should be forwarded? I n s t r. O r d e r add $1,$6,$2 add $1,$1,$3 add $5,$1,$4

  20. Corrected Data Forwarding Control Conditions • MEM/WB hazard: if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (EX/MEM.RegisterRd != ID/EX.RegisterRs) and (MEM/WB.RegisterRd = ID/EX.RegisterRs)) ForwardA = 01 if (MEM/WB.RegWrite and (MEM/WB.RegisterRd != 0) and (EX/MEM.RegisterRd != ID/EX.RegisterRt) and (MEM/WB.RegisterRd = ID/EX.RegisterRt)) ForwardB = 01

  21. Inserting bubbles Insert Bubble Hazard Detection Unit ID/EX EX/MEM WB M Control MEM/WB M u WB x 0 EX M WB PC IF/ID

  22. Datapath with Forwarding Hardware ID/EX EX/MEM Control IF/ID Add MEM/WB Branch Add 4 Shift left 2 Read Addr 1 Instruction Memory Data Memory Register File Read Data 1 Read Addr 2 Read Address PC Read Data Address Write Addr ALU Read Data 2 Write Data Write Data ALU cntrl 16 32 Sign Extend EX/MEM.RegisterRd ID/EX.RegisterRt Forward Unit MEM/WB.RegisterRd ID/EX.RegisterRs PCSrc

  23. Yoda says… Death is a natural part of life. Rejoice for those around you who transform into the Force. Mourn them do not. Miss them do not

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