Performed by: Nir Malka , Lior Rom Instructor: Mike Sumzik

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט (חלקא’/סופי) Subject: Project name Performed by: NirMalka , Lior Rom Instructor: Mike Sumzik סמסטר (חורף/קיץ) שנה 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract Design a high speed analog to digital daughter board which interfaces to Altera DE3. • Designing a new daughter board, which will interface to Altera DE3, and will be able to perform DAC and ADC sampling, at HS frequencies. • Preparing a manufacturing file, containing Orcad schematics, and main VHDL blocks. 2

3. Sample Real Time Digital Processing (DE3) Reconstruction Analog Input Analog Output High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Hardware • DC voltage supply: • Main DC power source from external DC supplier of 8.5V, into voltage regulators which output:AVDD 1.8V, AVDD3.3DRVDD 1.8V, DVDD3.3 • DC current consumption • ADC Supply Currents IAVDD < 203 mA • DAC Supply Currents IAVDD < 58mA • ADC Analog input signal: • Differential input voltage range: 1.25 Vp-p • Analog Input bandwidth: 70 MHz • Protection from Input over voltage (ESD) • ADC External clock input • Clock generator through SMA connector • Min conversion Rate 40 MSPS, 50% duty cycle • Differential Input voltage range < 6 Vp-p 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram 5

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram 50Mhz DE3 OSCILLATOR DATA FROM ADC DATA TO DAC USER INTERFACE CONFIGURATION 6