Integration Verification: Re-Create or Re-Use? Nick Gatherer Trident Digital Systems

1. Integration Verification: Re-Create or Re-Use? Nick GathererTrident Digital Systems

2. Introduction • Nick Gatherer • SoC Design Manager • Trident Digital Systems • (Formerly BU TV, NXP Semiconductors) • In former NXP role … • Chair of NXP’s Advanced Functional Verification Working Group • NXP’s cross-business expert team on verification • NXP Business Renewal project manager for System Level Design & Verification

3. Agenda Introduction & Verification Landscape Focus on Integration Verification Challenges What does it cost ? The IP  Integrator Interface Example verification re-use methodology Conclusions Q & A

4. Trident – SoCs for DTV & STB (high complexity !) • PNX85500 • Industry’s first digital TV processor in 45nm CMOS • Most complex SoC ever developed by NXP/Trident • Required aggressive TtM & Right First Time • From packaged parts received to System bring up in less than 10 days • Very high level of functionality and performance • PNX847x/8x/9x • World’s first fully integrated 45nm Set Top Box SoC platform • Architectural & IP re-use from PNX85500(internal & 3rd party IP)

5. Functional Verification – A Holistic Approach Verification Technology Landscape • Select appropriate platform per project phase • Availability vs Accuracy vs Performance vs Debuggability • Allocate coverage goals to specific platforms

6. Functional Verification – Re-Use Opportunities Re-use across verification tasks/abstractions Re-use across projects Re-use across verification platforms Verification Technology Landscape • Verification re-use depends on stakeholder alignment • IP suppliers, IP integrators, verification teams, technology/standards

7. Agenda Introduction & Verification Landscape Focus on Integration Verification Challenges What does it cost ? The IP  Integrator Interface Example verification re-use methodology Conclusions Q & A

8. Integration Verification – Challenges • HW integration verification • Focus on (structural) integration integrity • Interconnect & interoperability • Typical Challenges • Integrator has limited knowledge of IP implementation • IP supplier has limited knowledge of target system • Use of multiple IP suppliers results in inconsistent IP verification views • Methodology, testbenches, coverage data, etc. Industry standards late. • Mechanisms for accommodating IP configuration • Usually need to port IP tests to SoC level / environment in order to re-use • Huge effort ! What sub-set is needed for integration verification ? • Awareness and impact of IP implementation changes & known problems • Concurrent IP dev and SoC integration demands incremental maturity • Difficult to debug complex interactions between IPs (embedded checks help) • How much coverage is sufficient for integration confidence ?

9. Agenda Introduction & Verification Landscape Focus on Integration Verification Challenges What does it cost ? The IP  Integrator Interface Example verification re-use methodology Conclusions Q & A

10. Integration Verification – What does it cost per IP ? • Example project (from subsequent data mining) … Effort for integration verification is 50%-75% of the total SoC front end work  Re-use is a must!!!

11. Integration Verification – What does it cost per SoC ? • For a medium complexity SoC with around 50 IPs … Integration verification effort is 100 – 250 man weeks • Effort can vary a lot depending on how much integration verification can be re-used from previous projects • Effort can vary a lot depending on what is delivered by the IP provider (verification components) • Significant improvement potential on the IP provider side Design for integration verification • Significant improvement potential on the SoC integrator side Align on a common methodology Example project plan (based on 50% IP verification re-use) • Total effort reduced by 103 man weeks (approx 2 man years !)

12. Agenda Introduction & Verification Landscape Focus on Integration Verification Challenges What does it cost ? The IP  Integrator Interface Example verification re-use methodology Conclusions Q & A

13. IP  Integrator Interface for verification IP Datasheet (functionality, interfaces, etc) & Maturity index • Verification report … • IP verification strategy/plan & results (RTL, N/L, FPGA) • Code & functional coverage • Checklist/maturity, limitations, waivers, and open issues • Simulation vectors • Full & reduced set for integration Emulation models as needed to support mapping XML register description to support test creation Simulation models as needed to support testbench BFMs, eVC’s, OVC’s Interface & protocol assertion checkers IP specification & integration reviews (ideally face-2-face) Joint silicon bring-up & validation

14. Agenda Introduction & Verification Landscape Focus on Integration Verification Challenges What does it cost ? The IP  Integrator Interface Example verification re-use methodology Conclusions Q & A

15. Verification SW – Methodology Overview • Objective: • Enable IP suppliers to deliver IP integration tests • Implementation • Software-centric verification approach • ‘C’ tests run on any embedded processor (or transactor) • Non-invasive and runs on all implementation levels • SystemC, RTL, netlist, FPGA, emulation, silicon • API defined to ensure standard methodology • Allows IP supplier to define: • In-context connectivity verification test • Register tests can be generated automatically from IP-XACT metadata • Inter-operability test with generic platform functions • interrupt, DMA, clock, reset, power • IP context information is applied at the SoC integration phase • Allows automatic test program generation from suitable integration environment

16. IO-Stub IO-Stub SoC IOs IOs Logic IP IP CPU CPU Bus Interface Bus Interface VerificationSW VerificationSW DMA INTC CGU SoC Integrator(Chip context applied) Verification SW – Re-Use Example IP Supplier • IP supplier delivers STANDARDIZED verification components  Plug and Play Integration Verification

17. Agenda Introduction & Verification Landscape Focus on Integration Verification Challenges What does it cost ? The IP  Integrator Interface Example verification re-use methodology Conclusions Q & A

18. Conclusions • Verification continues to consume significant time & effort for complex SoCs • Design re-use is now well established • Verification re-use needs to catch up ! • IP is usually delivered with support for integration verification, but lacks consistency between suppliers • There’s a big difference between ‘re-usable’ and ‘almost re-usable’ ! • Proprietary approaches have emerged to overcome lack of industry standards, but these are not robust against industry dynamics • Overall …. • Design IP is a MUST • IP support for integration verification is a MUST • Need more standardisation of approach

19. Agenda Introduction & Verification Landscape Focus on Integration Verification Challenges What does it cost ? The IP  Integrator Interface Example verification re-use methodology Conclusions Q & A