“Location Based On-Chip Variation”

1. “Location Based On-Chip Variation” Rasit Onur Topaloglu University of California San Diego Computer Science and Engineering Department Ph.D. candidate www.cse.ucsd.edu/~rtopalog

2. Outline • Motivation • Process model • On-chip variation model • Validation methodology • Experimental Results • Conclusions

3. Motivation • Currently static timing analysis tools neglect cell locations Cell locations contain a valuable systematic information • Process variations, if not considered properly, may cause chips to fail or prone designs to be impossible to attain a spec. Increases design time and reduces yield

4. Oxide Distribution on Wafer 30cm wafer, 0.13m, SEM Oxide distribution seems to be circular & continuous Ref: Intel Technology Journal, Vol. 06, Issue 2, May 2002

5. Process and OCV Models

6. Cell speed Cell speed 1.05 1.1 1.2 1.15 Distance from center Distance from center Modeling of Process Variations : “Volcano Model” Equ-speed circles on wafer • Variation curves are circular • Linearly increasing or decreasing cell speeds along radius • Effects such as oxide variation, threshold voltage variation, lumped as cell speed variation

7. Process curves on chip chip1 -model -real 1 2 chip2 • Since chips are small, circle arcs approximated to be straight lines Modeling of On-chip Variation : “Angular Model” • Chip may fall anywhere on wafer C 1 • On-chip variation available as std. dev. only Assumption : max. on-chip speed variation • Cell speeds will be effected depending on angle wrt wafer center

8. Location of Chip Matters  C • Equ-lines are taken to be parallel to each other and normal to the line • that connects wafer center and closest corner of chip

9. Calculation of Speed Variation p  A B  |A//B| / |B| ratio is used to find process variation effect at location p • Multiply this ratio by maximum on-chip variation to find cell speed

10. B A 1.05 1.1 1.15 1.2 Hypothesis I : Chips at Same Angle if equ-speed circles not evenly distributed on wafer: • If process variation not linearly effecting cell speeds, maximum on-chip variations for chipA and chipB will differ • Chip2 has more variation, simulating for it is satisfactory

11. Hypothesis II : “Dominant Locations” on Wafer • Check a number of angles on wafer • We want other dies to pass too • Make sure simulating effects of process variations for dies on dominant locations is satisfactory

12. Test and Validation of Proposed Methods

13. Comparison Methodology Extract cell locations from Astro For each dominant location angle { Run script that changes cell speeds of a chip at a given angle and given max. on-chip variation Compare minimum setup times and hold times with a nominal run } Used to show that location based variations can be deteriorating as compared to worst-case runs

14. Comparison with Probabilistic Cell Speeds For each dominant location angle { Run script that changes cell speeds of a chip using a uniform distribution given max. on-chip variation Run script that changes cell speeds of a chip using a Gaussian distribution given max. on-chip variation Compare minimum setup times and hold times with a location based deterministic run } Used to show that location based variations can be deteriorating as compared to probabilistic models due to systematic variation

15. Proof I : Checking Validity of Method for Chips on Same Angle For a number of variations up to max on-chip variation { Run script that changes cell speeds of a chip at angle  } Compare minimum setup times and hold times  runs Used to show that for chips at same angle, simulating worst variation is satisfactory

16. Proof II : Checking Validity of Dominant Locations For a number of (angles \ dominant angles) { Run script that changes cell speeds of a chip given that angle Check that minimum setup or hold times are higher than found using dominant locations } Used to show that simulating for chips at dominant locations satisfactory for any location

17. 0.1242 when less variation used • Hypothesis I supported Experimental Results Setup (max delay) 0.1243 Nominal Location based 0.1001 Uniform random 0.1206 Gaussian random 0.1234 • Up to 20% variation in minimum slack observed on ARM7 • Or, try setting clock to 1GHz whereas your chip can run @ 800MHz on most locations on wafer

18. 1.74 3.92 5.15 1.74 -1.70 -3.29 1.71 1.40 0.53 0.53 max delays  paths max delays  paths for setup max data min clock delays for setup overest. underestimate Where Location Based Method fits in PrimeTime? WC TYP BC BC/WC OCV Setup (max delay) Hold (min delay) Location based falls here, more realistic than both directions

19. Conclusions • Dominant locations provide a means to reduce simulation time, yet integrate more accurate process variation effects • Probabilistic models fail to be satisfactory as they neglect deterministic systematic relationship between cells • Location based variation fits on a more realistic scale as compared to current PrimeTime models

20. Future Directions • Proper selection of dominant locations • Incorporation of interconnect delay variations A layout based mathematical approach