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Wafer Edge Exclusion. Kevin Fisher. Outline. What is Edge Exclusion? Motivation for reducing edge exclusion ITRS Roadmap Problems on the Edge Example: Copper Deposition. What is Edge Exclusion?. Edge of wafer considered unusable for a variety of reasons
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Wafer Edge Exclusion Kevin Fisher
Outline • What is Edge Exclusion? • Motivation for reducing edge exclusion • ITRS Roadmap • Problems on the Edge • Example: Copper Deposition
What is Edge Exclusion? • Edge of wafer considered unusable for a variety of reasons • Chips entirely on wafer but too close to edge are still invalidated
Yield Loss on the Edge • Current edge exclusion is 3mm • Reduces usable area of wafer by 2% • 300mm wafer: 70685 mm2 total area • 297mm usable area: 69279 mm2 • Area loss: 1406 mm2 • Athlon 64 die size: 144 mm2
Increasing Yield 300mm Pentium 4 Processor wafer (130nm)
ITRS on Edge Exclusion • Two references in 2003 Yield Enhancement report
Problems on the Edge • Chips, cracks, identification notches • Slurry/photoresist residue • Cleaning contaminants • Peeling films
Copper Interconnects • Two problems affect edges of wafers with copper metal layers • Barrier, seed layer residue • Copper islands
One Solution: Wet Processing Chambers • Apply film in liquid-filled chamber • Chemical breaks film’s surface tension