1 / 12

Agenda

Agenda. 目標與概述 (purpose) 架 構 (structure) 流程 (procedure) 成果 (result). Purpose. 學習目標： 學習VHDL標準規格與語法，以及相關輔助工具Xilinx ISE，並參與教育部大專院校積體電路設計FPGA組之比賽。 專題概述： 此專題為 直角三角形之直角座標轉譯系統，可將直角三角形的三個頂點座標 (x1,y1),(x2,y2),(x3,y3) 轉譯 ， 依續輸出涵蓋於直角三角形平面內的所有座標點。. Structure. 虛擬碼：. Procedure. 轉譯流程：

ardice
Download Presentation

Agenda

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Agenda • 目標與概述(purpose) • 架構(structure) • 流程(procedure) • 成果(result)

  2. Purpose • 學習目標： • 學習VHDL標準規格與語法，以及相關輔助工具Xilinx ISE，並參與教育部大專院校積體電路設計FPGA組之比賽。 • 專題概述： • 此專題為直角三角形之直角座標轉譯系統，可將直角三角形的三個頂點座標(x1,y1),(x2,y2),(x3,y3)轉譯，依續輸出涵蓋於直角三角形平面內的所有座標點。

  3. Structure • 虛擬碼：

  4. Procedure • 轉譯流程： • (1) 設定直角三角形座標。 • (2) 基準點從左下角開始，由左至右依序trace每個座標點。 • (3) 檢查是否超過右邊界，若尚未超過，則將該座標點儲存，若超過則基準點往上shift一個單位。 • (4) 檢查是否超過上邊界，若尚未超過則持續往右trace，若超過則結束trace，即完成轉譯。 • (5) 依序輸出每個座標點。

  5. State Diagram

  6. Code (input/output) entity triangle is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; xi : in STD_LOGIC_VECTOR (2 downto 0); yi : in STD_LOGIC_VECTOR (2 downto 0); nt : in STD_LOGIC; busy : out STD_LOGIC; po : out STD_LOGIC; xo : out STD_LOGIC_VECTOR (2 downto 0); yo : out STD_LOGIC_VECTOR (2 downto 0)); end triangle;

  7. Code • when mvr => xo <= xc; yo <= yc; po <= '1'; xc <= xc + 1; side <= (x2-xc)*(y3-y2)- (yc-y2)*(x2-x3); if side(7)='1' then xc <= x1; yc <= yc + 1; state_next <= mvu; end if;

  8. Code (cont.) • when mvu => xo <= xc; yo <= yc; xc <= xc + 1; side <= (x2-xc)*(y3-y2)- (yc-y2)*(x2-x3); if yc=y3 then state_next <= stop; elsif side(7)='1' then xc <= x1; yc <= yc + 1; state_next <= mvu; else state_next <= mvr; end if;

  9. Result • RTL Schematic Diagram (1)系統方塊：

  10. Result • RTL Schematic Diagram (2) ：

  11. Result • RTL Schematic Diagram (3) ：

More Related