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w7: sample hold circuits

Nov. 2nd, 2005. Basic Sample and Hold Circuit Configuration. ConceptMOSFET S

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w7: sample hold circuits

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    1. W7: Sample & Hold Circuits Insoo Kim Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Pennsylvania State University

    2. Nov. 2nd, 2005

    3. Nov. 2nd, 2005 Design Issues of CMOS S&H Sampling Moment Distortion Finite Clock rising/falling time results in distortion Clock Feed-through Overlap cap. of MOS Switch creates an sampling error during clock transition time MOS Switch Charge Injection Some charge in the MOS channel flow to Source and Drain, then result in an error.

    4. Nov. 2nd, 2005 Solutions for Reducing Sampling Distortion Differential S&H Circuit Sample Clock Bootstrapping Sampling distortion can be reduced by increasing clock amplitude

    5. Nov. 2nd, 2005 Sample Clock Bootstrap Circuits (I) Basic clock bootstrap circuit

    6. Nov. 2nd, 2005 Sample Clock Bootstrap Circuits (II) Differential sampling clock bootstrap circuit

    7. Nov. 2nd, 2005 Signal Dependent Clock Bootstrapping (I) The problem of clock bootstrap circuit Vgs of MOS switch can vary according to the input voltage level Ron of MOS Switch also vary It can cause an error in holding voltage Signal Dependent clock bootstrap circuit

    8. Nov. 2nd, 2005 Signal Dependent Clock Bootstrapping (II) Modified Circuit

    9. Nov. 2nd, 2005 Low Signal Feed-through Switch Schematic

    10. Nov. 2nd, 2005 Charge injection Compensation Switch (I)

    11. Nov. 2nd, 2005 Charge injection Compensation Switch (II)

    12. Actual Implementation S&H Circuits

    13. Nov. 2nd, 2005 Double Buffered S&H Configuration

    14. Nov. 2nd, 2005 Double Buffered S&H Circuit with CMOS Switch Schematic

    15. Nov. 2nd, 2005 Double Buffered S&H Circuit with CMOS Switch Simulation Result

    16. Nov. 2nd, 2005 Feedback Improved S&H Circuit

    17. Nov. 2nd, 2005 (cont’d) Feedback Improved S&H Circuit

    18. Nov. 2nd, 2005 (cont’d) Feedback Improved S&H Circuit

    19. Nov. 2nd, 2005 Integrating S&H Circuit

    20. Nov. 2nd, 2005 S&H Circuit using Miller Cap.

    21. Nov. 2nd, 2005 Switched Capacitor S&H Circuit Basic Configuration Common implementation for pipelined ADCs

    22. Nov. 2nd, 2005 References Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters- 2nd Edition,” Kluwer Academic Publishers, 2003. B. Razavi, “Principles of Data Conversion System Design,” IEEE Press, 1995.

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