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PHASE NOISE OF A Int -N PLL SYNTHESIZER

NOISE REDUCTION BY LOOP. PLL NOISE. TOTAL NOISE. VCO NOISE. 20Log(N/R). REF NOISE. Ref Noise. LOG SCALE. LOG SCALE. PHASE NOISE OF A Int -N PLL SYNTHESIZER. Noise Contributors in a Frac-N PLL. Example: 3 rd order MASH SD modulator, 3 rd order loop. “synth” noise. Ref. noise.

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PHASE NOISE OF A Int -N PLL SYNTHESIZER

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  1. NOISE REDUCTION BY LOOP PLL NOISE TOTAL NOISE VCO NOISE 20Log(N/R) REF NOISE Ref Noise LOG SCALE LOG SCALE PHASE NOISE OF A Int-N PLL SYNTHESIZER

  2. Noise Contributors in a Frac-N PLL Example: 3rd order MASH SD modulator, 3rd order loop “synth” noise Ref. noise VCO noise 20log(N/R) 20logN SD Noise Xtal Ref. Phase Noise PFD Noise floor = FOM+10log(fPFD) • To ensure far out noise is dominated by VCO performance… • SD modulator should have sufficient OSR (power penalty) • Pole at 1/R3C3 as low as possible (trade-off vs. loop stability margin)

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