Study of excess heat capacity and suppressed Kapitza conductance in TES devices

1. Study of excess heat capacity and suppressed Kapitza conductance in TES devices Y. Zhao, Cornell University, J. Appel, Princeton University, J. A. Chervenak, NASA GSFC, R. Doriese, NIST Boulder, S. Staggs, Princeton University

2. Anomalous behavior in “leg isolated” bolometers • Lueker – reports decoupling of TES from dielectric membrane in SiNspiderweb(IEEE Trans Appl. Supercon. 19 p 496 (2009)) • Excess heat capacity measurements in SiN / TES Kenyon, et. al., IEEE Trans Appl. Supercon. 19 p. 524 (2009) D. J. Goldie et. al. J. Appl. Phys. 105, 074512 (2009) Eckart, et. al., LTD-13, AIP conf. proc. 1185, 430 (2009) • We are studying the magnitude of these effects in a series of Si devices / possible relationship

3. Engineering decoupling into bolometers • Single crystal silicon for membrane • Devices side by side on same chip; with and without trench isolation near TES • Measure IV characteristic and impedance curves to extract all parameters in same environment (takes out common mode effects of fridge setup, readout electronics, magnetic field) 20 micron leg Local thermal Isolation for TES 1.055 mm2 Si TES

4. Detector Fabrication • SOI wafer (1.4 micron single crystal device layer) • Backetch to membrane, remove buried oxide in HF, release part in SF6 RIE Prior to frontetch Post frontetch Bias power for 32 pixels on single chip Pixel Params (1.055 mm2 Si) Expected values C(TES)~0.1 pJ/K [normal] C(Si)~0.1 pJ/K [Debye] GTS~7e5 pW/K [Kapitza calc] GTS~5e4 pW/K [empirical scaling] No decoupling below 100 kHz anticipated

5. Series of Four Test Devices A B C D Detector parameters from IV analysis

6. Models for Detector Impedance Model (a) – Ideal TES – Concentric Semicircles for Impedance Curves Model (b) locates the excess heat capacity in parallel with the TES, whereas Model (c) looks at a series heat capacity, such as one associated with the narrow legs

7. Model enables decoupling of components in electrothermal circuit • Fits for heat capacities (3), thermal conductances (3), a, b, (but not temperatures) • Allows for second heat capacity to be coupled (intended to be electrons in absorber film, though absorber is NOT on these devices) • Compare to measured impedance (swept sine method; Lindemann method for normalizing amplifier chain transfer function) • Extracts variations in Gts that were designed

8. Typical Impedance and quality of fit Three block fit better than two block, indicating presence of third time constant

9. Results from model • Model attempts to extract absolute numbers – but, for example, Cs + Ca is quite collosal (>10x) compared to Debye value for the volume of Si. • Gts of device 10x low compared to empirical value for metal to dielectric at these temps (100x lower than Kapitza calculation Au to Si).

10. 20 micron leg / 1 mm2 Si Pixel type “A” – No added perforation Models b and c both fit the top components (C_Si, G_TS, etc.) with same parameters Excess heat cap is higher for model c – series model

11. Establishing Confidence Intervals on extracted parameters • To compare parameter values among various devices • Bootstrapping method (random sampling of input data set) gives 5% error bars on 68% confidence interval on fit parameters • Rules out covariance, overfitting issues with method

12. Tabulated Data from Three Block Models Models fit to same impedance curves for Tbase=320 mK; 50% Rn

13. Excess heat capacity versus thermal decoupling in devices with same leg width (Dev A, B, C) Decoupling expected from introduction of stencils near TES Unexpected rise in heat capacity (greater than confidence interval of model)

14. Compare Devices B and D: different leg width Changing leg width causes changes in all internal parameters in supposedly identical structures

15. Data summary • Cs and sum of excess C correlated with Gts for devices where legs are same width; 15% C increase engineered with small slots in otherwise identical devices • Trend with narrower leg isolation is that total excess heat capacity is lower but its thermalization slower

16. Are model results consistent with contamination? • Observable contamination evident on surfaces of devices/ especially edges. (“Teflon” formed during silicon dry etch) • Heat cap changes without change in volume /surface area • Perim increases from A -> B->C (heat cap went up) • Perim increases from A ->D (heat cap dropped)

17. Speculation about Gts - Cs correlation • Phonons emitted by metal on dielectric can elastically scatter in the membrane until reabsorbed in the metal, suppressing measured GTS from Kapitza value • Since TES is constantly dissipative, persistence of population of excess phonons in silicon membrane region contribute to the statistical ensemble determining the heat capacity

18. Where’s the second heat capacity?(further speculation) • Effect of leg width on Gts may further imply long lived phonons; phonon modes that are elastically reflected into and out of leg (thus more weakly coupled) • That a large heat capacity is directly associated with TES NOT indicated by model (Ct is near constant in all models; Gts consistent with expectation)

19. Conclusion • 4 devices measured that show excess heat cap and thermal decoupling of metal from dielectric • Models further indicate Gts varies as expected; other internal parameters interact / vary unexpectedly • While small volume of teflon on device edges is visible, it does not match the model consistently in all four cases • Correlation of Gts with Cs & Ca suggests mechanism for intrinsic non-idealities of leg isolated TES