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Low power design: Insert delays to eliminate glitches

Low power design: Insert delays to eliminate glitches. Yijing Chen Dec.6, 2005 Auburn university. Components of Power. Dynamic Signal transitions Logic activity Glitches Short-circuit Static Leakage. Dynamic Power. Each transition of a gate consumes CV 2/2. Methods of power saving:

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Low power design: Insert delays to eliminate glitches

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  1. Low power design:Insert delays to eliminate glitches Yijing Chen Dec.6, 2005 Auburn university ELEC6970-001 Glitch Power

  2. Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage ELEC6970-001 Glitch Power

  3. Dynamic Power • Each transition of a gate consumes CV2/2. • Methods of power saving: • Minimize load capacitances • Transistor sizing • Library-based gate selection • Reduce transitions • Logic design • Glitch reduction ELEC6970-001 Glitch Power

  4. Glitch Power Reduction • Design a digital circuit for minimum transient energy consumption by eliminating hazards ELEC6970-001 Glitch Power

  5. Theorem • For correct operation with minimum energy consumption, a Boolean gate must produce no more than one event per transition. Output logic state changes One transition is necessary Output logic state unchanged No transition is necessary ELEC6970-001 Glitch Power

  6. Balanced Delay Method • All input events arrive simultaneously • Overall circuit delay not increased • Delay buffers may have to be inserted 4? 1 1 1 1 1 3 1 1 1 1 1 ELEC6970-001 Glitch Power

  7. Cell of multiplier Static power: 320.0184pW Average power: 107.1806uW ELEC6970-001 Glitch Power

  8. Simulation result of cell ELEC6970-001 Glitch Power

  9. Delay is added in the cell ELEC6970-001 Glitch Power

  10. Simulation result for delay is added ELEC6970-001 Glitch Power Static power: 568.6279pW average power: 144.8164uW

  11. Sum input B A Carry out Carry in Full adder Sum output B3 B2 B1 B0 0 0 0 0 A0 0 Y0 A1 0 Y1 A2 0 Y2 A3 0 Y7 Y6 Y5 Y3 Y4 Cell Array 4x4 multiplier ELEC6970-001 Glitch Power

  12. 4x4 multiplier simulation result Static power: 4.7694nW , average power:1.8339mW ELEC6970-001 Glitch Power

  13. Critical path j i Cell Mij has the longest delay path length of 2i+j+1 ELEC6970-001 Glitch Power

  14. Delay balanced multiplier cell ELEC6970-001 Glitch Power

  15. Modified 4X4 multiplier ELEC6970-001 Glitch Power

  16. Conclusion • The delay-balancing technique can be used on all types of parallel array multipliers such as Booth’s multiplier and Wallace Tree multiplier. • Achieves power reduction of 36% on a parallel array multiplier ELEC6970-001 Glitch Power

  17. Reference • Dr. AGRAWAL’s Elec 6970 slides • Gary Yeap (motorola) , Practical low power digital VLSI design, Kiuwer Academic publishers, 1998. ELEC6970-001 Glitch Power

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