TX79: A MIPS-Compatible Synthesizable Core with Multimedia Vector Extensions

1. TX79: A MIPS-Compatible Synthesizable Core withMultimedia Vector Extensions Peter Hsu Toshiba America Electronic Components, Inc.

2. System-On-a-Chip Challenges • Technical • High Performance Processor Core • Large System Complexity • Management • Intricate Back-End Process • Lingering Bug Fix Schedule • Business • Development Cost Containment

3. Toshiba’s SOC Solution • TX79 Processor Core • Dual Issue, 128-Bit SIMD Datapaths • Fully Synthesized, Standard Cells • System Architecture • Memory, Basic I/O Components • Physical Design Methodology • Absorb Last-Minute RTL Changes • Preserve Physical Timing Optimizations

4. Branch Target (32) 32 Words by 128 Bits Register File 64 Bit Exec Unit 64 Bit Exec Unit 128 Bit Memory Unit FPU 2-Scalar Dispatch 32KB I-Cache (2 Way) 32KB D-Cache (2 Way) 128 Bit Vector Unit TLB (48) RF (32) History (2K) Bus Interface Unit TX79 Block Diagram

5. TX79 Attributes • MIPS Architecture • 32 Bit Address • 64 Bit Data • 128 Bit Vector (ISA Extension) • Streaming Data • Nonblocking Prefetch • Efficient • 24mm2 (0.18um), 200MHz (w.c.)

6. UART Ethernet MAC PCI Controller System Architecture CPU Bus SDRAM Controller Processor Core Customer Logic Bridge Peripheral Bus (64 bits) SPI

7. Physical Design Challenges • Processor Core • Speed: Physically Based Optimizations • Flexibility: Shape, Routing Porosity • Migration: Standard Cells • Complex Integrated System • Manage Convergence • Lingering Bug Fixes

8. Tiles: Scalable Methodology • Necessity • Chip: 10M+ Gate • Tools: 1M Gate? • Multifaceted • Reusable Unit • Independent Construction • Fast Turnaround

9. RTL Tile P&R Synthesis Tile P&R Synthesis Tile P&R Synthesis Gate Level Netlist Floorplanner/Tiler GDSII Timing Analysis CAD Flow • “Master Plan” • Logical-Physical Gate Mapping • Tile Dimensions • Hard Macro Placement • Pin Locations • Parallel Flow

10. Tiles: Malleable, Reusable Unit • Can Be Hard Macro • Fixed, Dependable Timing • Quantifiably Finished • Can Be Reshaped • Preserves Physically-Based Speed Tuning Effort (Relatively) • Can Be Moved Around • CPU Core Shape Flexibility

11. Examples U Shaped TX79 L Shaped TX79

12. SOC Challenges Addressed • High Performance Processor Core • In Between Soft and Hard Macro • Physical Speed Tuning • Flexible Shape, Standard Cells • Complex System • Partitioned Construction Flow • Rapid “RTL to GDSII” for Bug Fixes • Manageable Process

13. Complete SOC Solution • Silicon Issues • Building Blocks • System Architecture • Construction Methodology • Other Issues • Chip Packaging • System Verification • Manufacturing Test

14. Chip Packaging • Integrated CAD • Artwork • I/O Cell Placement • Wire Bonding Coordinates • Global Design • PC Board, Package, Chip

15. Summary • TX79 Processor Core • Powerful Dual-Issue Pipeline • 128 Bit Multimedia Vector Operations • 200MHz, 24mm2 • Complete SOC Solution • Basic Building Blocks • System Architecture • Mature Methodology