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FPGA Encryption/Decryption System based on the Enigma Final Presentation

FPGA Encryption/Decryption System based on the Enigma Final Presentation. Written by: Yaakov Levenzon Ido Kahan Advisor: Mr. Mony Orbach. Spring Semester 2013. The Problem. We carry sensitive information with us, to practically everywhere…. Where is it?!. Project Goals.

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FPGA Encryption/Decryption System based on the Enigma Final Presentation

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  1. FPGA Encryption/Decryption System based on the EnigmaFinal Presentation Written by: Yaakov Levenzon Ido Kahan Advisor: Mr. Mony Orbach Spring Semester 2013

  2. The Problem We carry sensitive information with us, to practically everywhere… Where is it?!

  3. Project Goals • Primary Goal: • Creating a complete system which encrypts and deciphers files by using the method of the famous “Enigma” machine, while following the instructions of our part A system. • Didactic Goals: • Dealing with a design and implementation of a complete encryption/decryption system, thus strengthening our VHDL skills. • Implementing the Enigma system into our architecture (while using its generic ability to modify it for working with streams of data), in pipeline configuration.

  4. Part A - Development and Verification System Encryption system Enigma EncryptionDecryption AES EncryptsDecoder FIFO 128->8 PC CTRL CTRL PC-USB CTRL DLP Read enable from counter (gets AES enable) CTRL Nios Host Instruction Memory 4k bits USB protocol(1 MB/s) DE2 protocol FIFO 8->128 en from counter Valid_data_out 128 bit USB DLP CTRL FULL 8 8 bit 8 128 8 Min 16 words => 1 block cipher Key- 128 128 8 Key string- 128 Nios II/e FULL Register 128 bits One source file divided into small files Data Controller CLK freq: 200 MHz 1738 LES (5%) Total mem bits 43264 (9%) 16 bits data bus 1 MB/s data transfer rate to DLP 245M Uses the Avalon Bus AES enable FIFO read enable Clk (input)

  5. Instructions page for using our system (taken from our project A book) • Maximum possible Encryption/Decryption memory size: 221696 bits (46%) • (Recommended size – for 85% capacity: 149120 bits) • Maximum possible Encryption/Decryption number of LE: 32645 • Key Size: 128 bits • Data width: 128 bits • System speed: 1 MBPS (dictated by the DLP module) • DLP FIFO size: 1024 bits • DLP FIFO Speed: 384 byte Transmit buffer / 128 byte receive buffer

  6. The Enigma System • The original Enigma machine: • In our system: • More characters • More combinations • Start position to the ASCII table. • hopping method - Fibonacci function • Every day -> different key. • Plugboard. • Reflector.

  7. Encryption Data Flow – step 1 First rotor Second rotor . . . 0x01 0x02 0x03 0x04 0xFF 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC 0x14 0x98 0x76 0x94 0xE1 Encrypted data 0x02, 0x02 Ox4B, OxA2 PC PC ASCII table Key A ASCII table Key B 5 rotors

  8. Keys – step 2 94*5=470 PC RAM 0x85........0x23 0x680x540x430xA20x28 • Every rotor receives different key • The keys will be changed every day • The keys file will be saved in a safe file ASCII ASCII ASCII KEY A KEY B KEY C Second rotor Third rotor First rotor

  9. First Positions For The Rotors – step 3 • Another level of security • Every rotor have a different first-position • The first-positions will be changed every day a rotor a rotor 0x01 0x02 0x03 0x04 0xFF 0xFE 0xFF 0x01 0x02 0xFD Promote 2 steps ASCII table ASCII table

  10. First Positions– continue 5 PC RAM • Another level of security • Every rotor have a different first-position • The first-positions will be changed every day • Two separated files: keys and positions ASCII ASCII ASCII KEY A KEY B KEY C Second rotor Third rotor First rotor

  11. Hopping Method - Fibonacci Function - step 4 First rotor 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC 0x02, 0x02 0x4B, 0xA2 • f(x)=f(x-1)+f(x-2) • f(0) and f(1) is changing every day • The keys file contains two Initial conditions for every rotor f(x) ASCII table First key

  12. The Reflector - step 5 • Plugboard – changed every day • The problem is… Pipeline!!! Reflector fifth rotor 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC ASCII table ASCII table Key Plugboard

  13. The Reflector – second mind • Plugboard – changed every day Reflector Fifth rotor A Fifth rotor B . . . . . . 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC 0x01 0x02 0x03 0x04 0xFF 0x01 0x02 0x03 0x04 0xFF 0xA 0x4B 0x67 0x89 0xAC 0xA 0x4B 0x67 0x89 0xAC ASCII table ASCII table Key ASCII table Key Plugboard

  14. Decryption Algorithm • The encryption-system is symmetrical as the Enigma machine. • Should use the same keys (permutation), same positions for the keys and the same rotor-positions. First rotor First rotor 0x01 0x02 0x03 0x04 0xFF 0xA2 0x4B 0x67 0x89 0xAC . . . 0xA2 0x4B 0x67 0x89 0xAC 0x01 0x02 0x03 0x04 0xFF PC 0x4B, 0xA2 0x02, 0x02 Encrypted data First key ASCII table ASCII table First key

  15. Block Diagram – Encryption From project A FIFO-IN Rotor 1-A Rotor 2-A Rotor 3-A Rotor 4-A Rotor 5-A unencrypted Different key Reflector Rotor 5-B Rotor 4-B Rotor 3-B Rotor 2-B Rotor 1-B From project A FIFO-OUT encrypted

  16. Algorithm Golden Model • As instructed, we aimed to create a Golden Model to our algorithm in order to: strengthen our understanding of the algorithm, spot bugs early on, thus making the process of hardware design and implementation easier for us. • Each rotor can be individually debugged if necessary. Each key can be easily altered.Aimed to cover as much cases as possible (such as, repeated keys, uncommon ASCII chars, Fibonacci function as our implemented hopping function. • Modular and generic as possible: adding chars, keys, rotors, other hopping functions is possible with minimum effort. • Creating the keys for each day. • As documented and explained as we can, for further maintenance.

  17. Generic and modular - verification

  18. Encrypting a string - verification • Repeated input – unrepeated output

  19. Architecture – High Level DE2 FPGA controller Nios II Host PC DLP AVALON USB Enigma Out_Data FIFO In_Data FIFO

  20. Block Diagram – Writing to FPGA FPGA DLP PC FIFO Sending words Words by USB protocol Words on AVALON bus Unencrypted words PC PC Nios Nios FPGA DLP PC ENIGMA FIFO Words on AVALON bus Words by USB protocol Saving words Nios Nios PC PC Encrypting words Encrypted words • Reading from FPGA to the PC is the same data-flow • This data-flow is for Encrypting as well as for decrypting

  21. Top Level – project A+B The Enigma

  22. Top Level – The Enigma Reflector Control first rotor The rotor before the reflector The rotor after the reflector Mux 2->1 Last rotor

  23. Top Level- Compilation

  24. Timing Analysis Reg_out Reg_in 11 clocks • Latency – 13 clock cycles • Throuput – 1 clock cycle • Max frequency – 120 Mhz • => The bottleneck is the DLP!

  25. GUI for the user

  26. Bugs and new features learned • Enigma Golden Model – the windows.h library (in order to handle date functions)

  27. Bugs - Continue • The reflector problem • What is the trade-off? • Pros • Throuput – 1 clock cycle instead of 11. • The frequency has not Influenced. • Cons • Five more little memories (8*128=1k)

  28. Planning ahead • Improving our system: • Upgrading interfaces protocol to USB 2.0 (or even 3.0). • Upgrading the DLP (bigger FIFO, or a faster connector than our DLP). • Better hopping function – harder to decipher while easier to compute. • Trying to crack our Enigma machine: Designing and implementing a system that will attempt to decipher text encrypted by our system with as little knowledge as possible (constraints and pre-intelligence might be necessary – e.g. Second World War cracking process). • Encrypting the keys with a private key, while using other encryption algorithm – i.e. two step encryption process will make the system much stronger. • Encrypting videos, network transmissions, audio etc.

  29. Summary and conclusions • The project goals were fully accomplished. • We now comprehend that a target-oriented and generic development system can advance the design and implementation process, simplifying it while lowering costs and time-to-market. • The concept behind Enigma impressed us. It was one of the most sophisticated encryption/decryption systems of its time (recall, only human errors made it possible to decrypt in reasonable time). • CAD and the FPGA platform enabled us to strengthen the algorithm (unlimited wiring board, more chars, bigger key, and generic, rotating and variable rotors).Furthermore, it kept the system and its' sub-systems manageable and reusable. It also enabled us to add some exciting features, including picture encryption. • We enjoyed working on the project very much, and would like to thank our advisor, Mr. Mony Orbach.

  30. Thank you for listening

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