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Combinational Logic

Combinational Logic. Lecture #6. Decoder 3x8 Mux 4x1 Mux 8x1 Mux 8x1 4bits Half Adder Full Adder Ripple carry Adder 4-bit Adder. 강의순서. Combinational Logic. One or more digital signal inputs One or more digital signal outputs

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Combinational Logic

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  1. Combinational Logic Lecture #6

  2. Decoder 3x8 Mux 4x1 Mux 8x1 Mux 8x1 4bits Half Adder Full Adder Ripple carry Adder 4-bit Adder 강의순서 모바일컴퓨터특강

  3. Combinational Logic • One or more digital signal inputs • One or more digital signal outputs • Outputs are only functions of current input values (ideal) plus logic propagation delays i1 Combinational Logic O1 im On 모바일컴퓨터특강

  4. Combinational Logic (cont.) • Combinational logic has no memory • Outputs are only function of current input combination • Nothing is known about past events • Repeating a sequence of inputs always gives the same output sequence • Sequential logic does have memory • Repeating a sequence of inputs can result in an entirely different output sequence 모바일컴퓨터특강

  5. 합성(Synthesis) 구현(Implementation) Combinational Logic (cont.) • Design Procedure 회로 기능 명세 서술문 진리표를 이용한 정규논리식 정의 논리식 (Logic Expression) 카르노맵 등을 이용하여 논리식 단순화 최소화된 논리식 (Minimized Logic Expression) 하드웨어 논리회로 모바일컴퓨터특강

  6. (참고)Design Entry Flow with Quartus II 모바일컴퓨터특강

  7. Logic simplifications • Consider an automobile buzzer • Buzzer = (Key In and Door Open) or (Headlight On and Door Open) • B = KD + HD = (K+H)D 모바일컴퓨터특강

  8. Simulation • Verify if b_reduced yields the same result. 모바일컴퓨터특강

  9. Compilation Report • Verify the reduced equation with Fitter Equation & : AND ! : NOT # : OR $ : XOR 모바일컴퓨터특강

  10. Floorplan • Verify the reduced equation with Floorplan 모바일컴퓨터특강

  11. Exercise (1) • Simplify X = (ABC’ + B)BC’ by starting with a BDF • Verify the result with compilation report & floorplan 모바일컴퓨터특강

  12. Exercise (2) • Simplify the equations by starting with a VHDL file • X = (AB + (B’+C))’ • Y = (AB)’ + (B+C)’ • Verify the result with compilation report & floorplan 모바일컴퓨터특강

  13. Exercise (3) –Entering a Truth Table with VHDL • Identify the logic with compilation report & floorplan 모바일컴퓨터특강

  14. Decoder n • 3-to-8, 4-to–16, n–to–2 M0 M1 M7 A0 A1 A2 A typical 3 – to - 8 decoder circuit 모바일컴퓨터특강

  15. 3x8 Decoder (Signal assignment, Conditional) LIBRARY ieee; -- 3x8 decoder using Boolean equations-- USE ieee.std_logic_1164.ALL; ENTITY decoder_a IS PORT(a0,a1,a2 : IN std_logic; y0,y1,y2,y3,y4,y5,y6,y7 : OUT std_logic); END decoder_a ; ARCHITECTURE arc OF decoder_a IS BEGIN y0 <= (NOT a2) AND (NOT a1) AND (NOT a0); y1 <= (NOT a2) AND (NOT a1) AND ( a0); y2 <= (NOT a2) AND ( a1) AND (NOT a0); y3 <= (NOT a2) AND ( a1) AND ( a0); y4 <= ( a2) AND (NOT a1) AND (NOT a0); y5 <= ( a2) AND (NOT a1) AND ( a0); y6 <= ( a2) AND ( a1) AND (NOT a0); y7 <= ( a2) AND ( a1) AND ( a0); END arc; 모바일컴퓨터특강

  16. 3x8 Decoder (Signal assignment, Select; Truth Table) LIBRARY ieee; -- 3x8 decoder using vectors USE ieee.std_logic_1164.ALL; -- and selected signal assignment ENTITY decoder_b IS PORT(a : IN STD_LOGIC_VECTOR (2 downto 0); y : OUT STD_LOGIC_VECTOR (7 downto 0)); END decoder_b ; ARCHITECTURE arc OF decoder_b IS BEGIN WITH a SELECT y<="00000001" WHEN "000", "00000010" WHEN "001", "00000100" WHEN "010", "00001000" WHEN "011", "00010000" WHEN "100", "00100000" WHEN "101", "01000000" WHEN "110", "10000000" WHEN "111", "00000000" WHEN others; END arc; 모바일컴퓨터특강

  17. concatenate 3x8 Decoder with enable LIBRARY ieee; -- 3x8 decoder with enable -- USE ieee.std_logic_1164.ALL; ENTITY decoder_c IS PORT(en : IN std_logic; a : IN STD_LOGIC_VECTOR (2 DOWNTO 0); y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END decoder_c ; ARCHITECTURE arc OF decoder_c IS SIGNAL inputs : std_logic_vector(3 DOWNTO 0); BEGIN inputs<=en & a; WITH inputs SELECT y<="00000001" WHEN "1000", "00000010" WHEN "1001", "00000100" WHEN "1010", "00001000" WHEN "1011", "00010000" WHEN "1100", "00100000" WHEN "1101", "01000000" WHEN "1110", "10000000" WHEN "1111", "00000000" WHEN others; END arc; 모바일컴퓨터특강

  18. 같은 표현 d(2) <= d2; d(1) <= d1; d(0) <= d0; 3x8 Decoder (CASE) (1) library ieee; use ieee.std_logic_1164.all; entity decoder38_proc is port( d2, d1, d0 : in std_logic; y0,y1,y2,y3,y4,y5,y6,y7 : out std_logic); end decoder38_proc; architecture xxx of decoder38_proc is signal d : std_logic_vector(2 downto 0); signal t : std_logic_vector( 0 to 7); begin d <= d2&d1&d0; process(d) begin case d is when "000" => t<="10000000"; when "001" => t<="01000000"; when "010" => t<="00100000"; when "011" => t<="00010000"; when "100" => t<="00001000"; when "101" => t<="00000100"; when "110" => t<="00000010"; when others => t<="00000001"; end case; end process; y0 <= t(0); y1 <= t(1); y2 <= t(2); y3 <= t(3); y4 <= t(4); y5 <= t(5); y6 <= t(6); y7 <= t(7); end xxx; 회로보다는 설계사양에 관심을 둔 설계방식. 모바일컴퓨터특강

  19. 3x8 Decoder (CASE) (2) • Timing Simulation Result 모바일컴퓨터특강

  20. Mux 4x1(Signal Assignment, Conditional) library ieee; use ieee.std_logic_1164.all; entity mux41_ when is port( a, b, c, d: in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic); end mux41_ when; architecture a of mux41_when is BEGIN y <= a when (s=“00”) else b when (s=“01”) else c when (s=“10”) else d; END a; 모바일컴퓨터특강

  21. D0 D1 F D7 A B C MUX (Multiplexer) • 2N data input, • 1 data output, • N control inputs that select one of the data inputs. 모바일컴퓨터특강

  22. Mux 4x1(Signal Assignment, Selected) library ieee; use ieee.std_logic_1164.all; entity mux41_with is port( a, b, c, d: in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic); end mux41_with; architecture a of mux41_with is BEGIN WITH s SELECT y<= a WHEN "00", b WHEN "01", c WHEN "10", d WHEN others; END a; 모바일컴퓨터특강

  23. Mux 4x1 (IF) library ieee; use ieee.std_logic_1164.all; entity mux41_if_proc is port( a,b,c,d : in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic); end mux41_if_proc; architecture proc of mux41_if_proc is begin process(a,b,c,d,s) begin if( s="00") then y<=a; elsif( s="01") then y<=b; elsif( s="10") then y<=c; else y<=d; end if; end process; end proc; 모바일컴퓨터특강

  24. Mux 4x1 (case) library ieee; use ieee.std_logic_1164.all; entity mux41_case_proc is port( a,b,c,d : in std_logic; s : in std_logic_vector(1 downto 0); y : out std_logic); end mux41_case_proc; architecture proc of mux41_case_proc is begin process(a,b,c,d,s) begin case s is when "00" => y<=a; when "01" => y<=b; when "10" => y<=c; when others => y<=d; end case; end process; end proc; 모바일컴퓨터특강

  25. Decoder3_8.vhd는 미리 작성된 상태임 Mixed Modeling : structure + dataflow Mux 8x1 (Mixed Modeling) Library ieee; Use ieee.std_logic_1164.all; entity mux8_1 is port( a, b, c, d, e, f, g, h : in std_logic; s2, s1, s0 : in std_logic; y : out std_logic); end mux8_1; architecture xxx of mux8_1 is component decoder3_8 port( a, b, c : in std_logic; d0,d1,d2,d3,d4,d5,d6,d7 : out std_logic); end component; signal t : std_logic_vector(7 downto 0); signal d0,d1,d2,d3,d4,d5,d6,d7 : std_logic; begin U1: decoder3_8 port map( s2,s1,s0,d0,d1,d2,d3,d4,d5,d6,d7); t(0) <= a and d0; t(1) <= b and d1; t(2) <= c and d2; t(3) <= d and d3; t(4) <= e and d4; t(5) <= f and d5; t(6) <= g and d6; t(7) <= h and d7; y <= t(0) or t(1) or t(2) or t(3) or t(4) or t(5) or t(6) or t(7); end xxx; t(0) t(1) t(2) t(3) t(4) t(5) t(6) t(7) 모바일컴퓨터특강

  26. 같은 표현 sel(2) := s2; sel(1) := s1; sel(0) := s0; Mux 8x1 (Constants) library ieee; use ieee.std_logic_1164.all; entity mux8_1_proc is port( a,b,c,d,e,f,g,h : in std_logic; s2, s1, s0 : in std_logic; y : out std_logic); end mux8_1_proc; architecture proc of mux8_1_proc is constant bits3_0 : std_logic_vector(2 downto 0) := "000"; constant bits3_1 : std_logic_vector(2 downto 0) := "001"; constant bits3_2 : std_logic_vector(2 downto 0) := "010"; constant bits3_3 : std_logic_vector(2 downto 0) := "011"; constant bits3_4 : std_logic_vector(2 downto 0) := "100"; constant bits3_5 : std_logic_vector(2 downto 0) := "101"; constant bits3_6 : std_logic_vector(2 downto 0) := "110"; constant bits3_7 : std_logic_vector(2 downto 0) := "111"; begin process(a,b,c,d,e,f,g,h,s2,s1,s0) variable sel : std_logic_vector(2 downto 0); begin sel := s2 & s1 & s0; case sel is when bits3_0 => y<= a; when bits3_1 => y<= b; when bits3_2 => y<= c; when bits3_3 => y<= d; when bits3_4 => y<= e; when bits3_5 => y<= f; when bits3_6 => y<= g; when others => y<= h; end case; end process; end proc; 모바일컴퓨터특강

  27. Mux 8x14bits (Signal Assignment, Selected) library ieee; use ieee.std_logic_1164.all; entity mux81_4bits_with is port( a, b, c, d, e, f, g, h : in std_logic_vector(3 downto 0); s2, s1, s0 : in std_logic; y : out std_logic_vector(3 downto 0) ); end mux81_4bits_with; architecture a of mux81_4bits_with is signal s : std_logic_vector(2 downto 0); BEGIN s <= s2 & s1 & s0; -- s(2)<=s2; s(1)<=s1;s(0)<=s0; WITH s SELECT y <= a WHEN "000", b WHEN "001", c WHEN "010", d WHEN "011", e WHEN "100", f WHEN "101", g WHEN "110", h WHEN others; END a; 모바일컴퓨터특강

  28. Mux 8x14bits (case) library ieee; use ieee.std_logic_1164.all; entity mux81_4bits_proc is port( a,b,c,d,e,f,g,h : in std_logic_vector(3 downto 0); s2, s1, s0 : in std_logic; y : out std_logic_vector(3 downto 0)); end mux81_4bits_proc; architecture proc of mux81_4bits_proc is signal sel : std_logic_vector(2 downto 0); begin sel <= s2 & s1 & s0; process(a,b,c,d,e,f,g,h,sel) begin case sel is when "000" => y<= a; when "001" => y<= b; when "010" => y<= c; when "011" => y<= d; when "100" => y<= e; when "101" => y<= f; when "110" => y<= g; when others => y<= h; end case; end process; end proc; 모바일컴퓨터특강

  29. Half Adder (1) • Combinational logic circuits give us many useful devices. • One of the simplest is the half adder, which finds the sum of two bits. • Based on the truth table, we’ll construct the circuit. 모바일컴퓨터특강

  30. Half Adder (2) • The sum can be found using the XOR operation and the carry using the AND operation. • S = X  Y, C = XY 모바일컴퓨터특강

  31. Full Adder (1) • Full adder adds carry_in as well. • The truth table for a full adder is shown at the right. 모바일컴퓨터특강

  32. Full Adder (2)- Boolean expression S = m(1,2,4,7) = X’ Y’ Cin + X’ Y Cin’ + X Y’ Cin’ + X Y Cin = X’ (Y’ Cin + Y Cin’) + X (Y’ Cin’ + Y Cin) = X’ (Y  Cin) + X (Y  Cin)’ = X  Y  Cin Cout = m(3,5,6,7) = X’ Y Cin + X Y’ Cin + X Y Cin’ + X Y Cin = (X’ Y + X Y’) Cin + XY(Cin’ + Cin) = (X  Y) Cin + XY 모바일컴퓨터특강

  33. Full Adder (3) 모바일컴퓨터특강

  34. Full Adder (4) – using Half adder 모바일컴퓨터특강

  35. Ripple Carry Adder • Just as we combined half adders to make a full adder, full adders can be connected in series. • The carry bit “ripples” from one adder to the next; hence, this configuration is called a ripple-carryadder. ripple: 잔물결, 파문 Today’s systems employ more efficient adders. 모바일컴퓨터특강

  36. Ripple Carry Adder Operation • All 2n input bits available at the same time • Carries propagate from the FA in position 0 (with inputs x0 and y0) to position i before that position produces correct sum and carry-out bits • Carries ripple through all n FAs before we can claim that the sum outputs are correct and may be used in further calculations 모바일컴퓨터특강

  37. 4-bit Adder library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add_4bits_proc is port( a, b : in std_logic_vector(3 downto 0); s : out std_logic_vector(3 downto 0) ); end add_4bits_proc; architecture a of add_4bits_proc is begin s <= a+b; end a; + 연산자가 사용될 때 꼭 사용. Carry Out이 16이므로 14를 더하면 30이됨. 모바일컴퓨터특강

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