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Atributos de sinais

Atributos de sinais. sinal ‘last_value -- o valor do sinal antes do último evento nele sinal ‘event -- true no case de ocorrência de um evento no sinal , false caso contrário. signal clk : std_logic; signal y1, y2 : std_logic; y2 <= clk'last_value;

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Atributos de sinais

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  1. Atributos de sinais sinal‘last_value-- o valor do sinal antes do último evento nele sinal‘event-- trueno case de ocorrência de um evento no sinal, false caso contrário signal clk : std_logic; signal y1, y2 : std_logic; y2 <= clk'last_value; if (clk'event and clk = '1') then y <= x; endif;

  2. entity mux4_1 is Port ( x, y, z, w : in std_logic; o : out std_logic; sel : in std_logic_vector(1 downto 0)); end mux4_1; architecture Behavioral of mux4_1 is begin mux: process (sel) is begin if (sel = "00") then o <= x; elsif (sel = "01") then o <= y; elsif (sel = "10") then o <= z; else o <= w; end if; endprocess mux; end Behavioral; Atribuição concorrente de sinais atribuição condicional architecture Behavioral of mux is begin o <= x when sel = "00" else y when sel = "01" else z when sel = "10" else w when sel = "11"; end Behavioral;

  3. entity mux_case is Port ( x, y, z, w : in std_logic; o : out std_logic; sel : in std_logic_vector(1 downto 0)); end mux_case; architecture Behavioral of mux_case is begin mux: process (sel) is begin case sel is when "00" => o <= x; when "01" => o <= y; when "10" => o <= z; whenothers => o <= w; endcase; endprocess mux; end Behavioral; Atribuição concorrente de sinais atribuição selectiva architecture Behavioral of mux is begin with sel select o <= x when "00", y when "01", z when "10", w whenothers; end Behavioral;

  4. Atribuição concorrente e agregados entity full_adder is Port ( a : in std_logic; b : in std_logic; cin : in std_logic; s : out std_logic; cout : out std_logic); end full_adder; architecture Behavioral of full_adder is begin with std_logic_vector'(a, b, cin) select (cout, s) <= std_logic_vector'("00") when "000", std_logic_vector'("01") when "001", std_logic_vector'("01") when "010", std_logic_vector'("10") when "011", std_logic_vector'("01") when "100", std_logic_vector'("10") when "101", std_logic_vector'("10") when "110", std_logic_vector'("11") whenothers; end Behavioral; um somador completo de 1 bit

  5. architecture Behavioral2 of entidade is signal a, b, c : std_logic; begin or2_1: process (x(1), x(2)) is begin a <= x(1) or x(2); endprocess or2_1; inv: process (x(3)) is begin b <= not x(3); endprocess inv; or2_2: process (b, x(2)) is begin c <= b or x(2); endprocess or2_2; and2_1: process (a, c) is begin y <= a and c; endprocess and2_1; end Behavioral2; entity entidade is Port ( x : in std_logic_vector(3 downto 1); y : out std_logic); end entidade; architecture Behavioral1 of entidade is begin y <= (x(1) or x(2)) and (x(2) ornot x(3)); end Behavioral1;

  6. entity and2 is Port ( x : in std_logic; y : in std_logic; z : out std_logic); end and2; architecture b of and2 is begin z <= x and y; end b; entity or2 is Port ( x : in std_logic; y : in std_logic; z : out std_logic); end or2; architecture b of or2 is begin z <= x or y; end b; entity inv is Port ( i : in std_logic; o : out std_logic); end inv; architecture b of inv is begin o <= not i; end b; architecture structural of entidade is signal a, b, c : std_logic; begin or2_1: entity work.or2(b) portmap (x => x(1), y => x(2), z => a); inv: entity work.inv(b) portmap (i => x(3), o => b); or2_2: entity work.or2(b) portmap (x => b, y => x(2), z => c); and2_1: entity work.and2(b) portmap (x => a, y => c, z => y); end structural;

  7. Descrição parametrizável entity gen_mux is Port ( vector : in std_logic_vector; sel : in std_logic_vector; o : out std_logic); end gen_mux; architecture beh of gen_mux is begin o <= vector(conv_integer(sel)); end beh; entity muxes is Port ( vector1 : in std_logic_vector (3 downto 0); vector2 : in std_logic_vector (7 downto 0); sel1 : in std_logic_vector (1 downto 0); sel2 : in std_logic_vector (2 downto 0); o1, o2 : out std_logic); end muxes ; architecture structural of muxes is begin en1: entity work.gen_mux(beh) port map( vector => vector1, sel => sel1, o => o1); en2: entity work.gen_mux(Behavioral) port map( vector => vector2, sel => sel2, o => o2); end structural;

  8. entity gen_mux is generic ( n : natural := 7; k : natural := 2); Port ( vector : in std_logic_vector (ndownto 0); sel : in std_logic_vector (kdownto 0); o : out std_logic); end gen_mux; architecture beh of gen_mux is begin o <= vector(conv_integer(sel)); end bef; Generic entity muxes is Port ( vector1 : in std_logic_vector (3 downto 0); vector2 : in std_logic_vector (7 downto 0); sel1 : in std_logic_vector (1 downto 0); sel2 : in std_logic_vector (2 downto 0); o1, o2 : out std_logic); end muxes; architecture structural of muxes is begin en1: entity work.gen_mux(beh) genericmap (n => vector1'high, k => sel1'high) portmap( vector => vector1, sel => sel1, o => o1); en2: entity work.gen_mux(bef) genericmap (n => vector2'high, k => sel2'high) portmap( vector => vector2, sel => sel2, o => o2); end structural;

  9. Componentes

  10. instanciação directa de entidades entityedge_trig_Dffis Port ( clk : in std_logic; clr : in std_logic; d : in std_logic; q : out std_logic); end edge_trig_Dff; architecturesimpleof edge_trig_Dff is begin q <= '0' when clr = '1' else d when rising_edge(clk); end simple; entity reg4 is Port ( clk, clr : in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0)); end reg4; architecture estrutural of reg4 is begin bit0:entity work.edge_trig_Dff (simple) portmap (clk, clr, d(0), q(0)); bit1:entity work. edge_trig_Dff (simple) portmap (clk, clr, d(1), q(1)); bit2:entity work. edge_trig_Dff (simple) portmap (clk, clr, d(2), q(2)); bit3:entity work. edge_trig_Dff (simple) portmap (clk, clr, d(3), q(3)); end estrutural;

  11. declaração do componente instanciação do componente architecture struct of reg4 is component edge_trig_Dff is Port ( clk : in std_logic; clr : in std_logic; d : in std_logic; q : out std_logic); endcomponent edge_trig_Dff; begin bit0: component edge_trig_Dff portmap (clk => clk, clr => clr, d => d(0), q => q(0)); bit1: component edge_trig_Dff portmap (clk => clk, clr => clr, d => d(1), q => q(1)); bit2: component edge_trig_Dff portmap (clk => clk, clr => clr, d => d(2), q => q(2)); bit3: component edge_trig_Dff portmap (clk => clk, clr => clr, d => d(3), q => q(3)); end struct;

  12. especificação da configuração das instâncias do componente architecture struct of reg4 is component DFF is Port ( clk : in std_logic; clr : in std_logic; d : in std_logic; q : out std_logic); endcomponent DFF; forall : DFF useentity work.edge_trig_Dff(simple); begin bit0: component DFF portmap (clk => clk, clr => clr, d => d(0), q => q(0)); bit1: component DFF portmap (clk => clk, clr => clr, d => d(1), q => q(1)); bit2: component DFF portmap (clk => clk, clr => clr, d => d(2), q => q(2)); bit3: component DFF portmap (clk => clk, clr => clr, d => d(3), q => q(3)); end struct;

  13. será utilizada esta arquitectura Configurações normalmente não são suportadas pelas ferramentas de síntese. Caso não exista nenhuma configuração explícita, vai ocorrer a ligação por defeito (default binding): para cada instância de cada componente será seleccionada uma entidade cujos nome, portas, etc. coincidam com a declaração da componente. Se a entidade tiver mais que uma arquitectura, será seleccionada aquela que foi analisada o mais recentemente. architecturesimpleof edge_trig_Dff is begin q <= '0' when clr = '1' else d when rising_edge(clk); end simple; architecturesimple2of edge_trig_Dff is begin q <= '0' when clr = '1' else (not d) when rising_edge(clk); end simple2; architecturesimple3of edge_trig_Dff is begin q <= '0' when clr = '1' else '1' when rising_edge(clk); end simple3; component edge_trig_Dff is Port ( clk : in std_logic; clr : in std_logic; d : in std_logic; q : out std_logic); endcomponent edge_trig_Dff;

  14. entity top is Port ( clk, rst : in std_logic; ext_rw, cs_lcd, csn_lcd, ext_a : out std_logic; ext_d : out std_logic_vector(7 downto 0)); end top; architecture struct of top is componentBUFGP port (I: in std_logic; O: out std_logic); endcomponent BUFGP; componentreg4is Port ( clk, clr : in std_logic; d : in std_logic_vector(3 downto 0); q : out std_logic_vector(3 downto 0)); endcomponent reg4; componentlcd_reg port ( clk48, rst : in std_logic; ext_a, ext_rw, cs_lcd, csn_lcd : out std_logic; ext_d : out std_logic_vector(7 downto 0); reg : in std_logic_vector(3 downto 0) ); endcomponent lcd_reg; signal clk48, nrst : std_logic; signal reg_data : std_logic_vector (3 downto 0); IBUFG + BUFG

  15. entity top is Port ( clk, rst : in std_logic; ext_rw, cs_lcd, csn_lcd, ext_a : out std_logic; ext_d : out std_logic_vector(7 downto 0)); end top; begin nrst <= not rst; clock_buffer : BUFGP portmap (I => clk, O => clk48); registo : reg4 portmap (clk => clk48, clr => nrst, d => "0100", q => reg_data); LCD : lcd_reg portmap (clk48 => clk48, rst => rst, ext_a => ext_a, ext_d => ext_d, ext_rw => ext_rw, cs_lcd => cs_lcd, csn_lcd => csn_lcd, reg => reg_data); end struct;

  16. Instanciação de primitivas É possível instanciar componentes específicos da arquitectura sem haver necessidade de especificar a sua definição. Estes componentes são referenciados por primitivas no Libraries Guide:

  17. Geração estrutural entity gen_reg is generic (w : natural); Port ( clk, clr : in std_logic; d : in std_logic_vector (wdownto 0); q : out std_logic_vector(wdownto 0)); end gen_reg; architecture struct of gen_reg is component edge_trig_Dff is Port ( clk, clr, d : in std_logic; q : out std_logic); endcomponent edge_trig_Dff; begin gen_reg: for i in 0 to w generate bits: component edge_trig_Dff portmap (clk => clk, clr => clr, d => d(i), q => q(i)); endgenerate gen_reg; end struct; component gen_reg is generic (w : natural); Port ( clk, clr : in std_logic; d : in std_logic_vector(w downto 0); q : out std_logic_vector(w downto 0)); endcomponent gen_reg; registo : gen_reg genericmap (w => reg_data'high) portmap (clk => clk48, clr => nrst, d => "0100", q => reg_data);

  18. É também possível utilizar comando generate para descrever modelos comportamentais. entity proc_gen is port ( clk : in std_logic; vector : in std_logic_vector(1 to 3); result : out std_logic_vector(1 to 3)); end proc_gen; architecture Behavioral of proc_gen is type matrix isarray (1 to 3, 1 to 3) of std_logic; constant transf_matrix : matrix := ( 1 => ('1', '1', '0'), 2 => ('0', '1', '1'), 3 => ('1', '0', '1') ); begin transformation: for i in 1 to 3 generate process (clk) is begin result(i) <= (transf_matrix(i,1) and vector(1)) or (transf_matrix(i,2) and vector(2)) or (transf_matrix(i,3) and vector(3)); endprocess; endgenerate transformation; end Behavioral;

  19. Geração condicional entityhalf_addis port ( a, b : in std_logic; sum, cout : out std_logic); end half_add; architecture descr of half_add is begin sum <= a xor b; cout <= a and b; end descr; entityfull_addis port ( a, b, cin : in std_logic; sum, cout : out std_logic); end full_add; architecture descr of full_add is begin sum <= a xor b xor cin; cout <= (a and b) or (a and cin) or (b and cin); end descr; Construir um somador genérico que não tem a entrada de carry (ripple-carry adder with no carry-in)

  20. entitygen_addis generic (w : natural); port ( a, b : in std_logic_vector(w downto 0); r : out std_logic_vector(w downto 0); cout : out std_logic); end gen_add; architecture struct of gen_add is component full_add port (a, b, cin : in std_logic; sum, cout : out std_logic); endcomponent; component half_add port (a, b : in std_logic; sum, cout : out std_logic); endcomponent; signal carry : std_logic_vector(w downto 0); .....

  21. begin gen_som: for i in 0 to w generate lower_bit: if i = 0 generate u0: half_add portmap (a => a(i), b => b(i), sum => r(i), cout => carry(i)); endgenerate lower_bit; upper_bits: if i > 0 generate ux: full_add portmap (a => a(i), b => b(i), cin => carry(i - 1), sum => r(i), cout => carry(i)); endgenerate upper_bits; endgenerate gen_som; cout <= carry(w); end struct; somador : gen_add genericmap (w => reg_data'high) portmap (a => "0100", b => "0011", r => reg_data, cout => open);

  22. Estruturas recursivas Determinação de paridade de um vector. ...

  23. entity rec is generic (w : natural := 7); port ( d : in std_logic_vector (w downto 0); z : out std_logic); end rec; architecture recursive of rec is signal l, r : std_logic; begin simple_tree : if w = 1 generate begin z <= d(0) xor d(1); endgenerate simple_tree; comp_tree : if w > 1 generate begin left :entity work.rec(recursive) genericmap ((w-1)/2) portmap (d => d((w-1)/2 downto 0), z => l); right:entity work.rec(recursive) genericmap ((w-1)/2) portmap (d => d(w downto (w-1)/2 + 1), z => r); z <= l xor r; endgenerate comp_tree; end recursive;

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