Org Remarks; building the computer (i.e. processor)

1. Org Remarks; building the computer (i.e. processor) • Work in teams on the remainder of the processor assignment • Work incrementally on the processor assignment • Don’t hesitate to ask questions and to ask for help! • Understanding how to build the processor, how to program in machine language, and in its assembly language will go a long way!!!!!! Digital Techniques Fall 2007 André Deutz, Leiden University

2. Org Remarks; building the computer (i.e. processor) • Recall: the summary of a d-flip-flop • In the implementation with Digital Works: use the built-in edge triggered d-flip-flop of DW for any of the state elements (such as registers, program counter, data-memory etc). Digital Techniques Fall 2007 André Deutz, Leiden University

3. Orgrem: Why should you keep a design notebook? Make it On-line • Keep track of the design decisions and the reasons behind them • Otherwise, it will be hard to debug and/or refine the design • Write it down so that you can remember in long project: 2 weeks ->2 yrs • Others can review notebook to see what happened • Record insights you have on certain aspect of the design as they come up • Record of the different design & debug experiments • Memory can fail when very tired • Industry practice: learn from others’ mistakes

4. Orgrem: Content of the On lineDesign Note Book • Top 10 things to put in your on-line design notebook • 10. Start: type “date” and copy & paste into your notebook. • 9. What is the goal/objective of today? • 8. Description of any problem: what did you see? what did you do? • 7. Keep track of the time whenever you do a new “compile.” • 6. Procedures for testing and running experiments. • 5. Outputs of tests and experiments. • 4. Insights and thoughts you have while you work. • 3. Copy & paste headers of important emails. • 2.. Last thing of the day: One line summary => Notebook Index. • 1. Finish: type “date” and copy & paste into your notebook. Digital Techniques Fall 2007 André Deutz, Leiden University

5. The Big Picture: Where are We Now? Processor Input Control Memory Datapath Output • The Five Classic Components of a Computer • Today’s Topic: Datapath Design Digital Techniques Fall 2007 André Deutz, Leiden University

6. building our processor/computer • Our toy will help us to understand The von Neumann model • Utterly useful; also useful for the following courses: dite, computer architecture, operating systems, assembly language, machine language, assemblers, …. • We focus on Single-cycle computer: Digital Techniques Fall 2007 André Deutz, Leiden University

7. define: Single-cycle datapath All instructions execute in a singlecycle of the clock (positive edge to positive edge) Advantage: a great way to learn CPUs. Drawbacks: unrealistic hardware assumptions, slow clock period

8. Instruction Set of Our Tiny Mips computer • NB as powerful as C++ • Obviously far less expressive than C++ Digital Techniques Fall 2007 André Deutz, Leiden University

10. Get acquainted with the instruction set of TM • Write a program which computes the sum of 3 and 4. • Write a program (using looping/repetition) which computes the sum of the first three integers • Write a program which determines the largest of two numbers. • There is a canonical (not always efficient) of translating high level language (say C++) constructs (selection and repetition) into assembly language

11. A solution for the addition of the first three natural numbers. Assume that we also have an unconditional branch instruction ‘br L’ with the meaning: PC  L And less important: we also assume that we have the stop instruction called halt. A solution: Address instruction comment 0 ldi reg1, 1 const 1 1 ldui reg1, 0 make sure reg1 contains 1 2 ldi reg2, 0 reg2 accumulates sum 3 ldui reg2, 0 make sure reg2 contains 0 4 ldi reg3, 3 reg3 corresponds to the upper limit of iterations 5 ldui reg3, 0 make sure reg3 contains 0 6 ldi reg0, 0 reg0 is the counter 7 ldui reg0,0 make sure reg0 contains 0 8 add reg0, reg1 bump counter 9 add reg2, reg0 accumulate sum A seq reg0, reg3 set condition B breq D if eq {PC  D} C br 8 br {PC  8} D halt

12. Single cycle data paths: Assumptions All state elements act like positive edge-triggered flip flops. D Q clk Processor uses synchronous logic design (a “clock”). Reset ? Digital Techniques Fall 2007 André Deutz, Leiden University

13. A portion of the datapath used for Fetching instructions and incrementing The program counter (PC) Instr Mem Addr Data + 0x1 PC D Q

14. opcode operand1 operand2

15. Data flow on pos edge • The following slides show the data flows for most instructions such as: or, and, add, sub

16. How data flows after posedge op RegFile Instr Mem 2 rs1 4 4 2 rd1 rs2 2 Addr Data ws 4 4 ALU + Logic rd2 wd 0x1 WE 4 4 PC D Q Digital Techniques Fall 2007 André Deutz, Leiden University

17. Dataflow on pos edge • The following slide shows the dataflow with a minor adjusment for instructions such as ldi and ldui (for one of the sources a a 4-bit wide 4 to 1 mux (a better name would be: data selector) is used

18. How data flows after posedge (detail: adjustment for ldi and ldui instructions) Instr Mem Addr Data + Logic 0x1 4 4 4 4 PC D Q 4 ALU source op Data selector (mux) 4 RegFile 2 rs1 4 2 rd1 4 ALU rs2 2 ws 4 rd2 4 wd WE 4 Digital Techniques Fall 2007 André Deutz, Leiden University

19. How data flows after posedge (detail: adjustment for ldi and ldui instructions) Instr Mem Addr Data + Logic 0x1 4 4 4 4 PC D Q 4 ALU source op Data selector (mux) 4 RegFile 2 rs1 4 2 rd1 4 ALU rs2 2 ws 4 rd2 4 wd WE 4 Digital Techniques Fall 2007 André Deutz, Leiden University

20. Register File Chooses one of Registers 4-bit register 4-bit register 4-bit register 4-bit register to read Data by reading from First chosen register Selects a second register to read Chooses register to be written Data by readig from Second chosen register Data to be written Write Enable Digital Techniques Fall 2007 André Deutz, Leiden University Digital Techniques Fall 2007 André Deutz, Leiden University

21. Rough idea on implementation in DW • The following slide gives a rough idea how the datapath for the instructions is implemented (except ld, st and addi) • NB: our specification requires the breq to be implemented with absolute addressing (that is the address of the next to be executed instruction is contained in L (and PC gets L) when the branch is taken, as opposed to relative addressing: PC gets PC+L) when the branch is taken)

22. NB: breq is implemented with relative addressing