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Learning Outcome

EEE2243 Digital System Design Chapter 9: Advanced Topic: Physical Implementation by Muhazam Mustapha extracted from Frank Vahid’s slides, May 2012. Learning Outcome.

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Learning Outcome

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  1. EEE2243Digital System DesignChapter 9: Advanced Topic:Physical Implementationby Muhazam Mustapha extracted from Frank Vahid’s slides,May 2012

  2. Learning Outcome • By the end of this chapter, students are expected to understand some methodologies in IC production and aware about the current fabrication techologies

  3. Chapter Content • Application Specific IC (ASIC) • Field Programmable Gate Array (FPGA) • Other Technologies: • 74 Series • SPLD • PLD

  4. ASIC

  5. Manufactured IC Technologies C us t om l a y out F ab mo n ths IC • We can manufacture our own IC • Months of time and millions of dollars • (1) Full-custom or (2) semicustom • (1) Full-custom IC • We make a fullcustom layout • Using CAD tools • Layout describes the location and size of every transistor and wire • A fab (fabrication plant) builds IC for layout • Hard! • Fab setup costs ("non-recurring engineering", or NRE, costs) high • Error prone (several "respins") • Fairly uncommon • Reserved for special ICs that demand the very best performance or the very smallest size/power B elt W a r n k p w s

  6. Gate Array ASIC k p s ( d ) ( c ) IC F ab w eeks ( justwi r ing) • (2) Semicustom IC • "Application-specific IC" (ASIC) • (a) Gate array or (b) standard cell • (2a) Gate array • Series of gates already layed out on chip • We just wire them together • Using CAD tools • Vs. full-custom • Cheaper and quicker to design • But worse performance, size, power • Very popular B elt W a r n k p w s ( b ) ( a ) w

  7. Gate Array ASIC a'b ab' • (2a) Gate array • Example: Mapping a half-adder to a gate array Half-adder equations: s = a'b + ab' co = ab a c o ab b s G a t e a r r a y

  8. FPGA

  9. Programmable IC Technology – FPGA • Manufactured IC technologies require weeks to months to fabricate • And have large (hundred thousand to million dollar) initial costs • Programmable ICs are pre-manufactured • Can implement circuit today • Just download bits into device • Slower/bigger/more-power than manufactured ICs • But get it today, and no fabrication costs • Popular programmable IC – FPGA • "Field-programmable gate array" • Developed late 1980s • Though no "gate array" inside • Named when gate arrays were very popular in the 1980s • Programmable in seconds

  10. FPGA Internals: Lookup Tables (LUTs) F = x'y' + xy 4x 2 Mem. G = xy' 4x 1 Mem. 1 rd x y F G 1 rd 1 0 10 0 1 0 0 1 0 0 1 00 1 0 0 1 0 0 0 2 01 2 0 1 0 0 1 x=0 1 3 10 3 1 a1 a1 x 1 1 1 0 a0 y a0 D1 D0 D y=0 F=1 F G c d e ( ) ( ) ( ) • Basic idea: Memory can implement combinational logic • e.g., 2-address memory can implement 2-input logic • 1-bit wide memory – 1 function; 2-bits wide – 2 functions • Such memory in FPGA known as Lookup Table (LUT) F = x'y' + xy 4x 1 Mem. x y F 1 rd 0 0 1 0 0 1 0 1 1 0 0 2 1 1 1 3 a1 x a0 y D F a b ( ) ( )

  11. FPGA Internals: Switch Matrices Switch matrix 2-bit memory s1 s0 m0 i0 m1 o0 i1 4x 1 m2 d i2 mux m3 i3 o0 o1 m0 2-bit m1 memory m2 m3 Switch s1 s0 matrix i0 o1 i1 4x 1 d i2 mux i3 b ( ) • Previous slides had hardwired connections between LUTs • Instead, want to program the connections too • Use switch matrices (also known as programmable interconnect) • Simple mux-based version – each output can be set to any of the four inputs just by programming its 2-bit configuration memory FPGA (partial) 8x 2 Mem. 8x 2 Mem. 0 00 0 00 1 00 1 00 2 00 2 00 P0 3 00 3 00 P6 P1 a2 a2 4 00 4 00 a1 a1 P2 P7 5 00 5 00 a0 a0 P3 6 00 6 00 7 00 7 00 D1 D0 D1 D0 P8 P9 P4 P5 a ( )

  12. FPGA Internals: Configurable Logic Blocks (CLBs) CLB output flip-flop 1-bit 1 0 1 0 1 0 1 0 CLB 0 0 0 0 2x 1 2x 1 2x 1 2x 1 output configuration memory • LUTs can only implement combinational logic • Need flip-flops to implement sequential logic • Add flip-flop to each LUT output • Configurable Logic Block (CLB) • LUT + flip-flops • Can program CLB outputs to come from flip-flops or from LUTs directly FPGA CLB CLB 8x 2 Mem. 8x 2 Mem. 0 00 0 00 1 00 1 00 2 00 2 00 P0 3 00 3 00 P1 a2 a2 4 00 4 00 a1 a1 P2 o0 00 5 00 5 00 a0 a0 P3 o1 m0 00 m1 6 00 6 00 m2 7 00 7 00 m3 Switch D1 D0 D1 D0 matrix P6 P7 P8 P9 P4 P5

  13. FPGA Internals: Sequential Circuit Example using CLBs 11 00 10 01 01 10 00 11 0 00 00 a 10 00 00 b 11 00 00 00 00 1 1 1 1 z y x w c d FPGA a b c d CLB CLB 8x 2 Mem. 8x 2 Mem. 0 0 1 1 2 2 0 3 3 a2 a2 4 4 w x y z a1 a1 o0 5 5 a ( ) a0 a0 o1 m0 m1 6 6 m2 7 7 m3 Left lookup table Switch D1 D0 D1 D0 matrix a2 a1 a0 D1 D0 0 a b w=a' x=b' 0 0 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 0 2 x1 2 x1 2 x1 2 x1 0 1 0 0 1 0 1 1 0 0 below unused b ( ) c ( )

  14. FPGA Internals: Overall Architecture • Consists of hundreds or thousands of CLBs and switch matrices (SMs) arranged in regular pattern on a chip Connections for just one CLB shown, but all CLBs are obviously connected to channels Represents channel with tens of wires CLB CLB CLB SM SM CLB CLB CLB SM SM CLB CLB CLB

  15. Other Technologies

  16. 7400 Series • Off-the-shelf logic (SSI) IC • Logic IC has a few gates, connected to IC's pins • Known as Small Scale Integration (SSI) • Popular logic IC series: 7400 • Originally developed 1960s • Back then, each IC cost $1000 • Today, costs just tens of cents V C C I 14 I 13 I 12 I 11 I 10 I 9 I 8 I C I 1 I 2 I 3 I 4 I 5 I 6 I 7 GND

  17. 7400 Series

  18. 7400 Series n k p n w s b ( ) (b) Decompose into 2-input AND gates • Example: Seat belt warning light using off-the-shelf 7400 ICs • Option 1: Use one 74LS08 IC having 2-input AND gates, and one 74LS04 IC having inverters (a) Desired circuit 14 13 12 11 10 9 8 I I I I I I I k (c) Connect ICs to create desired circuit p 74LS08 C I w s 1 2 3 4 5 6 7 I I I I I I I w k a ( ) p 14 13 12 11 10 9 8 I I I I I I I s 74LS04 C I 1 2 3 4 5 6 7 I I I I I I I c ( )

  19. 7400 Series 0 k p w 0 s b ( ) Converting to 3-input NOR gates • Example: Seat belt warning light using off-the-shelf 7400 ICs • Option 2: Use a single 74LS27 IC having 3-input NOR gates k p w s w 14 13 12 11 10 9 8 I I I I I I I s k a ( ) 74LS27 C I p 1 2 3 4 5 6 7 I I I I I I I 0 c ( ) Connecting the pins to create the desired circuit

  20. Simple Programmable Logic Devices (SPLDs) 1 2 3 I I I • Developed 1970s (thus, pre-dates FPGAs) • Prefabricated IC with large AND-OR structure • Connections can be "programmed" to create custom circuit • Circuit shown can implement any 3-input function of up to 3 terms • e.g., F = abc + a'c' O1 PLD C I programmable nodes

  21. SPLD – Programmable Nodes 1 2 3 I I I O1 PLD C I programmable nodes • Fuse based – "blown" fuse removes connection • Memory based – 1 creates connection p r o g r ammable node Fuse based ( a ) F use "unbl o wn" fuse "bl o wn" fuse Memory based mem mem 1 0 ( b )

  22. PLD Extensions 1 2 3 1 2 3 I I I I I I programmable bit O1 O1 2 × 1 FF O2 O2 2 × 1 FF PLD C PLD C I I clk a b ( ) ( ) Two-output PLD PLD with programmable registered outputs

  23. More on PLD-s • Originally (1970s) known as Programmable Logic Array – PLA • Had programmable AND and OR arrays • AMD created "Programmable Array Logic" – "PAL" (trademark) • Only AND array was programmable (fuse based) • Lattice Semiconductor Corp. created "Generic Array Logic – "GAL" (trademark) • Memory based • As IC capacities increased, companies put multiple PLD structures on one chip, interconnecting them • Become known as Complex PLDs (CPLD), and older PLDs became known as Simple PLDs (SPLD) • GENERAL difference of SPLDs vs. CPLDs vs. FPGAs: • SPLD: tens to hundreds of gates, and usually non-volatile (saves bits without power) • CPLD: thousands of gates, and usually non-volatile • FPGA: tens of thousands of gates and more, and usually volatile (but no reason why couldn't be non-volatile)

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