Minor change and Research Schedule

1. RPS Minor change andResearch Schedule m5151117 Yumiko Kimezawa

2. Outline RPS • Previous Work • Current Work • Research Schedule • Future Work

3. Previous Work RPS • Investigation of BANSMOM System • Need to divide Master CPU memory into inst. mem and data mem • Need to use off-chip memory JTAG UART : Data flow : Control signal Graphic LCD LED FPGA Graphic LCD Controller External Memory ECG Data Slave CPU Slave CPU Memory DMA controller LED Controller Avalon Bus Timer Shared Memory Master CPU Master CPU Memory FIR Filter Timer Master Module PPD Module

4. Previous Work RPS • Investigation of BANSMOM System • Need to divide Master CPU memory into inst. mem and data mem • Need to use off-chip memory JTAG UART : Data flow : Control signal Graphic LCD LED FPGA Graphic LCD Controller External Memory ECG Data Slave CPU Slave CPU Memory DMA controller LED Controller Avalon Bus Timer Shared Memory Master CPU Inst Mem Data Mem FIR Filter Timer Master Module PPD Module

5. Previous Work RPS • Investigation of BANSMOM System • Need to divide Master CPU memory into inst. mem and data mem • Need to use off-chip memory JTAG UART : Data flow : Control signal Graphic LCD LED FPGA Graphic LCD Controller External Memory ECG Data Slave CPU Slave CPU Memory DMA controller LED Controller Avalon Bus Timer Shared Memory Master CPU Inst Mem Data Mem FIR Filter Timer Master Module PPD Module

6. Current Work RPS • Minor change

7. Current Work RPS Before modification After modification

8. Research Schedule RPS • Optimization of hardware • Optimization of software • Verification of the system • Writing master’s thesis

9. Future Work RPS • Optimization of hardware • Execution of software program

10. RPS

11. Investigation of BANSMOM System RPS • CPU memory • Until now • Instructions and data are in the same space • Minor change • Instructions and data are in different spaces Instruction cache: Write back is not required Data cache: Write back is required Inefficient Use of cache becomes efficient through separating these memories

12. Investigation of BANSMOM System RPS • Memory size (in 1-lead system’s case) • Master CPU instruction memory: 64Kbyte • Master CPU data memory: 32KByte • PPD CPU instruction memory: 32KByte • PPD CPU data memory: 32KByte • Shared memory: 2Kbyte • Program size • Master module: 55 Kbyte (code + initialized data) • PPD module: 16 Kbyte (code + initialized data) • Now, on-chip memory is used in the system • CPU instruction and data memory make up a most portion of memory of the system

13. Requirement RPS • BANSMOM system needs a lot of cache memory Use of off-chip memory as not only shared memory but also cache memory will be required

14. Investigation of Stratix III Board RPS Off-chip memory • DRAM • DDR3 SDRAM • DDR2 SDRAM • DDR SDRAM • QDRII + SRAM • QDRII SRAM • PLDRAM II • SRAM • QDR I/QDR II • NBT/Nobl • I’m trying to investigate • Memory capacity • How to use off-chip memory • Which memory to use

15. Future Work RPS • Optimization of BANSMOM system • investigate • Finish adding off-chip memory to our system

16. Investigation of Stratix III Board RPS • Embedded memory • M9K memory block: 355 • M144K memory block: 16 • Embedded memory: 5,499 Kbit • MLAB: 1,775 Kbit

17. Program Size RPS • 1-lead system • Master module • 55 Kbyte (code + initialized data) • PPD module • 16 Kbyte (code + initialized data) • 2-lead system • Master module • 56 Kbyte (code + initialized data) • PPD module • 16 Kbyte (code + initialized data) • PPD module 2 • 16 Kbyte (code + initialized data)