Chapter 6 Digital System Design

1. Chapter 6Digital System Design 242-208 Digital Systems and Logic Designs

2. Content Programmable Logic Devices (PLDs) PLD programming Combinational PLDs Sequential PLDs Field programmable gate arrays (FPGAs) Systematic Design ASM methods and charts Controller and data processor designs References

3. Design is more economical to implement using a few Large chips than many small chips. Design and fabrication time for VLSI chips are extremely long PLD can be mage in large volume and PROGRAMMED to implement large numbers of different low-volume designs PLD: Why we need ?

4. An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to perform different functions Two PLD types which are : SPLD (Simple PLD) CPLSs (Complex PLD) What is PLD ?

5. Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle layer, the amorphous silicon is turned into polysilicon, which is conductive. PLD programming methods: Antifuse technology After

6. Current cannot passed since no channel for carrier charge. Potential energy is still high !! PLD programming methods: Floating gate UV light strikes electrons, causes more enough energy for electrons to j ump back to the channel, The transistor starts conducting !! High voltage applied to the Drain, electrons jump to gate 1 Used in EPROM device !!

7. PLD programming methods: SRAM

8. Programmable Read Only Memory (PROM) : A memory device that stores data at specific locations that can be addressed through a set of address pins. Another view : a large array of AND gates followed by a large array of OR gates Combinational PLD:PROM

9. Programmable Logic Array (PLA) : Both arrays of logic AND and OR are programmable Combinational PLD:PLA

10. Programmable Array Logic (PAL) consists of a programmable array of AND gates that connect to a fixed array of OR gates The PAL structure allows any SOP expression with a defined number of variables to be implemented Combinational PLD:PAL

11. Combinational PLD:PAL

12. A PAL that can be reprogrammed. Combinational PLD:GAL

13. Consists of combinational PLDs with a set of FFs. See the diagram of IC PAL16R8. Sequential PLD:

14. Implement three-bit Gray code counter using PAL16R8 Sequential PLD:

15. Complex PLD • Programmable PLD blocks • Programmable interconnects • Electrically erasable links

16. Why we need FPGA ? Field Programmable Gate Array Limited complexity Thousands of gates Cheap and easy to design Reprogrammable Large complex functions(millions gates) Customised design Expensive to design (in small quantities) Hard to design and long design cycles Not reprogrammable High risks

17. Why we need FPGA ? Field Programmable Gate Array Inexpensive Easy and rapid design Prototyping Reprogrammable

18. Simple programmable Logic blocks Massive of programmable interconnects Field Programmable Gate Array FPGA architecture

19. Slice Xilinx FPGA: CLB CLB

20. Xilinx FPGA: CLB

21. Xilinx FPGA: CLB

22. Look up table FF, registers, clock storage elements MUX FPGA CLB FPGA architecture CLB

23. LUT contains memory cells to implement logic function Each cell holds ‘0’ or ‘1’ Programmed with outputs of truth table Inputs select content of one of the cells as output FPGA CLB with Look Up Table

24. 4 input – 16 outputs LUT requires 16 storage elements with 16 latches. What is in a LUT ?

25. Larger logic functions built by connecting many CLBs together FPGA CLB

26. Connections routing signals between CLBs Determined by SRAM cells Programmable routing

27. Programmable routing

28. Switch matrix Programmable routing

29. FPGA : I/O Blocks

30. For circuit design: • small circuit : gate-level design (truth tables, K maps, etc) • large circuit : block-level design (ICs) • Larger digital systems need more abstract and systematic design techniques. • Systematic design methodology : • Top-down approach • Partitioning • Developing overall architecture • Detailing hardware. Systematic Design

31. Starting from original problem and gradually refine it towards solution. • Steps for a top-down design procedure: • Specify the problem clearly (at global/top level without unnecessary details). • Break the problem into smaller sub-problems. • Repeat the process until sub-problems are small enough to be solved directly. Systematic Design : Top-down approach

32. Relevant to goal-directed approach • State goal, then find sub-goals to solve main goal. • Repeat until sub-goals are directly solvable. Systematic Design : Top-down approach

33. Status condition Commands Data Processor (Architecture) Control unit (Controller) External command Input data Output data • A digital system consists of two components • A control algorithm (Controller) • An architecture (Data processor) Systematic Design : Partitioning

34. Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems to obtain “control” and “data processor” units. • Major differences from flowcharts are: • only three box types:- • 1) state box (similar to operation box), • 2) decision box • 3) conditional box • contains exact (or precise) timing information while flowcharts impose a relative timing order for the operations. ASM

35. binary code state one or more operations • State box • Rectangular shape • One entry point and one exit point • Used to specify one or more operations which could be simultaneously completed in one clock cycle. Components of ASM chart

36. deciding factors deciding factors • Decision box • Diamond in shape • One entry point but multiple exit points • Used to specify a number of alternative paths that can be followed. Components of ASM chart

37. conditional operations • Conditional box • Rectangle with rounded corners • Always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box. Components of ASM chart

38. T0 Initial state 0 S 1 A  0 F  0 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 T2 1 F  1 Init S=0 if S equal 1 { A = 0 F = 0 } increase A if A2 equal 1 { E =1 if A3 equal 1 { F = 1 } } Example of using ASM chart

39. Registers present in the data processor for storing and processing data. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers. • The register operations are specified in either the state and/or conditional boxes, and are written in the form: destination registerfunction(other registers) Register operation

40. T0 Initial state 0 S 1 A  0 F  0 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 T2 1 F  1 • Precise timing is implicitly presented in ASM charts. • Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle. • A group of boxes which occur within a single clock cycle is called an ASM block. Timing in ASM charts

41. Operations of ASM can be illustrated through a timing diagram. • Two factors which must be considered are • operations in an ASM block occur at the same time in one clock cycle • decision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block) Timing in ASM charts

42. T0 Initial state 0 S 1 A0 F0 AA+1 E0 AA+1 E1 A  0 F  0 Operations AA+1 E0 AA+1 E1 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 AA+1 E0 F1 Operations T2 1 F  1 AA+1 E0 AA+1 E1 Timing in ASM charts A = A4A3A2A1

43. From ASM chart, we can synthesize • Controller logic (via State Table/Diagram) • Architecture/Data Processor • Design of controller is determined from the decision boxes and the required state transitions. • Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes. Digital system synthesis

44. Step 1: Identify all states and assign suitable codes. • Step 2: Draw state diagram. • Step 3: Formulate state table using State from state boxes Inputs from decision boxes Outputs from operations of state/conditional boxes. • Step 4: Obtain state/output equations and draw circuit. Controller synthesis procedure

45. T0 Assign codes to states: T0 = 00 T1 = 01 T2 = 11 T0 T1 T2 Initial state 0 S 1 A  0 F  0 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 Inputs from conditions in decision boxes. Outputs = present state of controller. T2 1 F  1 Controller synthesis

46. Decoder + D flip-flops • -suitable for moderately large controllers. • - procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection. Controller synthesis • The flip-flop input functions can be obtained directly from the state table by inspection. • This is because for the D flip-flops, • the next state = flip-flop D input. • Decoder is then used to provide signals to represent different states.

47. G1 ? D Q T0 2x4 decoder T1 G0 D ? unused Q T2 clock Controller synthesis • Given the state table: The inputs of the D flip-flops for G1 and G0 are DG1= T1.A2.A3 DG0= T0.S + T1

48. A2 G1 D Q A3 T0 2x4 decoder T1 G0 D unused Q S T2 clock Controller synthesis

49. Architecture is more difficult to design than controller. • Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine: • What registers to use • How they can be connected • What operations to support • How these operations are activated. • Guidelines: • always use high-level units • simplest architecture possible. Data processor synthesis

50. T0 Initial state 0 S 1 A  0 F  0 T1 A  A + 1 0 1 A2 E  0 E  1 0 A3 T2 1 F  1 • Various operations are: • Counter incremented (A  A + 1) when state = T1. • Counter cleared (A  0) when state = T0 and S = 1. • E is set (E  1) when state = T1 and A2 = 1. • E is cleared (E  0) when state = T1 and A2 = 0. • F is set (F  1) when state = T2. • Deduce: • One 4-bit register A • (e.g.: 4-bit synchronous counter with clear/increment). • Two flip-flops needed for E and F • (e.g.: JK flip-flops). Data processor synthesis