Global Timing Constraints

1. Global Timing Constraints FPGA Design Flow Workshop

2. Objectives After completing this module, you will be able to: • Apply global timing constraints to a simple synchronous design • Specify global timing constraints with the Constraints Editor

3. Outline • Introduction • Global Constraints • The Constraints Editor • Summary

4. Timing Constraints and Your Project What effects do timing constraints have on your project? • The implementation tools do not attempt to find the place & route that will obtain the best speed • Instead, the implementation tools try to meet your performance expectations • Performance expectations are communicated with timing constraints • Timing constraints improve the design performance by placing logic closer together so shorter routing resources can be used • Note that when we discuss using the Constraints Editor, we are referring to the Xilinx Constraints Editor

5. Without Timing Constraints • This design had no timing constraints or pin assignments • Note the logical structure of the placement and pins • This design has a maximum system clock frequency of 50 MHz

6. With Timing Constraints • This is the same design with three global timing constraints entered with the Constraints Editor • It has a maximum system clock frequency of 60 MHz • Note that most of the logic is placed closer to the edge of the device, where the pins have been placed

7. More About Timing Constraints • Timing constraints should be used to define your performance objectives • Tight timing constraints will increase your compile time • Unrealistic constraints will cause the implementation tools to stop • Use the synthesis report or the Post-Map Static Timing Report to determine whether your constraints are realistic • After implementing, review the Post-Place & Route Static Timing Report to determine whether your performance objectives were met • If constraints were not met, use the Timing Report to determine the cause

8. Path End Points • Two types of path end points: • I/O pads • Synchronous elements (flip-flops, latches, and RAMs) • Creating a timing constraint is a two-step process: • Step 1: Create groups of path end points • Step 2: Specify a timing requirement between the groups • Global constraints use default groups of path end points • All flip-flops, all I/O pads, etc.

9. FLOP1 FLOP2 FLOP3 D Q D Q D Q FLOP5 FLOP4 D Q D Q = Combinatorial Logic Review Questions • A single global constraint can cover multiple delay paths • If the arrows are constrained paths, what are the path end points in this circuit? • Do all of the registers have anything in common? ADATA OUT1 CLK BUFG OUT2 BUS [7..0] CDATA

10. FLOP1 FLOP2 FLOP3 D Q D Q D Q FLOP5 FLOP4 D Q D Q Answers • What are the path end points in this circuit? • FLOP1, FLOP2, FLOP3, FLOP4, and FLOP5 • Do all of the registers have anything in common? • They share a clock signal. A constraint that references this net could constrain all delay paths between all of the registers in the design ADATA OUT1 CLK BUFG OUT2 BUS [7..0] CDATA

11. Outline • Introduction • Global Constraints • The Constraints Editor • Summary

12. FLOP1 FLOP2 FLOP3 D Q D Q D Q FLOP5 FLOP4 D Q D Q The PERIOD Constraint • The PERIOD constraint covers paths between synchronous elements clocked by the reference net • The PERIOD constraint does NOT cover paths from input pads to output pads (purely combinatorial), from input pads to synchronous elements, or from synchronous elements to output pads ADATA OUT1 CLK BUFG OUT2 BUS [7..0] CDATA

13. Features of the PERIOD Constraint • The PERIOD constraint uses the most accurate timing information so it can automatically account for: • Clock skew between the source and destination flip-flops • Synchronous elements clocked on the negative edge • Unequal clock duty cycles • Clock input jitter • Assume: • 50-percent duty signal on CLK • PERIOD constraint of 10 ns • Because FF2 will be clocked on the falling edge of CLK, the path between the two flip-flops will actually be constrained to 50% of 10 ns = 5 ns FF1 FF2 CLK BUFG INV

14. Clock Input Jitter • Clock input jitter is one source of clock uncertainty • Clock uncertainty is subtracted from: • PERIOD constraint setup paths • OFFSET IN constraint setup paths • Clock uncertainty is added to: • PERIOD constraint hold paths • OFFSET IN constraint hold paths • OFFSET OUT constraint paths

15. The Pad-to-Pad Constraint • Purely combinatorial delay paths do not contain any synchronous elements • Purely combinatorial delay paths start and end at I/O pads and are often left unconstrained

16. Review Questions • Which paths are constrained by a PERIOD constraint on CLK1? • Which paths are constrained by a pad-to-pad constraint? FLOP LATCH PADA OUT1 D Q D Q G CLK1 PADB BUFG RAM D OUT2 CLK2 BUFG PADC

17. Answers • Which paths are constrained by a PERIOD constraint on CLK1? • FLOP to LATCH • Which paths are constrained by a pad-to-pad constraint? • PADC to OUT2 FLOP LATCH PADA OUT1 D Q D Q CLK1 G PADB BUFG RAM D OUT2 CLK2 BUFG PADC

18. FLOP D The OFFSET Constraint • The OFFSET constraints cover paths: • From input pads to synchronous elements (OFFSET IN) • From synchronous elements to output pads (OFFSET OUT) OFFSET IN OFFSET OUT FLOP FLOP ADATA OUT1 Q D Q D Q CLK BUFG FLOP FLOP D Q D Q OUT2 BUS [7..0] = Combinatorial Logic CDATA

19. Features of the OFFSET Constraint • The OFFSET constraint automatically accounts for the clock distribution delay • Provides the most accurate timing information • Increases the amount of time for input signals to arrive at synchronous elements (clock and datapaths are in parallel) • Reduces the amount of time for output signals to arrive at output pins (clock and datapaths are in series) • The OFFSET constraint also accounts for clock input jitter • Uses the jitter defined on the associated PERIOD constraint

20. T_data_Out T_data_In In Out T_clk_In T_clk_Out Clk OFFSET-IN OFFSET-OUT Clock Delay • Both the datapath delay and the clock distribution delay are used to calculate OFFSET constraints • OFFSET IN = T_data_In - T_clk_In • OFFSET OUT = T_data_Out + T_clk_Out Page 3

21. Review Question • Which paths are constrained by an OFFSET IN and an OFFSET OUT constraint in this circuit? FLOP LATCH PADA D Q D Q OUT1 G CLK BUFG RAM PADB OUT2 PADC

22. Answer • Which paths are constrained by an OFFSET IN and an OFFSET OUT constraint in this circuit? • OFFSET IN: PADA to FLOP and PADB to RAM • OFFSET OUT: LATCH to OUT1, LATCH to OUT2, and RAM to OUT1 FLOP LATCH PADA D Q D Q OUT1 G CLK BUFG RAM PADB OUT2 PADC

23. Outline • Introduction • Global Constraints • The Constraints Editor • Summary

24. Launching the Constraints Editor • In the Processes for Source window, expand User Constraints • Double-click Create Timing Constraints

25. Entering PERIOD and Pad-To-Pad Constraints • The PERIOD and pad-to-pad constraints can be made on the Global tab • Double-click here to make a PERIOD constraint • Global pad-to-pad constraint • Constraints can be deleted by selecting the constraint in the text window and pressing <Delete>

26. PERIOD Constraint Options • TIMESPEC name • Specific constraint value • Active clock edge • Duty-cycle • Relative to another PERIOD constraint • Useful for designs with multiple clock signals • Can define both frequency and phase relationships • Input jitter

27. Entering OFFSET Constraints • Global OFFSET IN/OUT constraints can also be made on the Global tab Pad to setup = OFFSET IN Clock to pad = OFFSET OUT

28. Outline • Introduction • Global Constraints • The Constraints Editor • Summary

29. Upstream Device Downstream Device 2 ns 3 ns Review Question • Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz? • Assume no clock skew between devices

30. Upstream Device Downstream Device 10 ns 8 ns 7 ns 2 ns 3 ns Answer • Given the system diagram below, what values would you put in the Constraints Editor so that the system will run at 100 MHz? • Answer: PERIOD = 10 ns , OFFSET IN = 7 ns and OFFSET OUT = 8 ns

31. Summary • Performance expectations are communicated with timing constraints • The PERIOD constraint covers delay paths between synchronous elements • The OFFSET constraint covers delay paths from input pins to synchronous elements and from synchronous elements to output pins • The Constraints Editor allows you to create timing constraints

32. Where Can I Learn More? • Timing Presentation on the Web at http://support.xilinx.com • Documentation  Technical Tips  Timing & Constraints  Getting Started  The Timing Presentation • Timing Improvement Wizard on the Web at http://support.xilinx.com • Click the Problem Solvers menu