280 likes | 439 Views
A New Tool for Designer-Level Verification: From Concept to Reality. April 30, 2014. Ziv Nevo IBM Haifa Research Lab. Overview. Designer-level verification (DLV) DLV tools: historical perspective at IBM Our latest recipe. Designer-level verification (DLV). Life without DLV. RTL. spec
E N D
A New Tool forDesigner-Level Verification: From Concept to Reality April 30, 2014 Ziv Nevo IBM Haifa Research Lab
Overview Designer-level verification (DLV) DLV tools: historical perspective at IBM Our latest recipe
Life without DLV RTL spec ---------- spec ---------- Verification engineer Logic designer
Weeks later… fail trace spec ---------- spec ---------- Verification engineer Logic designer
DLV ≈ “Developer testing”(standard practice in SW) RTL Verification engineer Logic designer Basic checks
What activities does DLV include? Debugging Lightweight verification Observation Checking assertions and coverage points Bug hunting Exploring corner cases Observing mainstream behavior
Verification: tools of the trade Simulator Testbench HVL Methodology Scripts Formal Assertions Coverage … Verification engineer Logic designer
DLV: what should the tools be? • Simulator • Testbench • HVL • Methodology • Scripts • Formal • Assertions • Coverage • … Logic designer
Idea 1: TIMEDIAG (1997) Specify input value/function/random Loop cycle (count/random/condition)
Idea 1: TIMEDIAG (1997) GenRand • Random instantiation • Simulation • Checking
TIMEDIAG ingredients What’s missing? • Interactive define/run/view • Event-guided test cases • Formal analysis Waveform-based interface simulation complex interleavings
What activities does DLV include? Debugging Lightweight verification Observation Checking assertions and coverage points Bug hunting Exploring corner cases Observing mainstream behavior
Idea 2: PathFinder (2002) Find a trace(formal analysis) View trace Define events
Idea 2: PathFinder (2002) Main flow: • Specify events • Find trace • View trace Minor feature: • Edit inputs on waveform • Simulate
PathFinder ingredients waveform-based interface simulation What’s missing? • Simple driving(default is random) • Fast simulation • Integration with common tools Event-guided test cases Formal analysis Interactive define/run/view
What activities does DLV include? Debugging Lightweight verification Observation Checking assertions and coverage points Bug hunting Exploring corner cases Observing mainstream behavior
Latest recipe: Diver Main flow Specify inputs Specify expected results scenario editor Simulate View trace View unexpected results IBM Debug and Verification Tool for Designers (DIVER)
Latest recipe: Diver Additional variations Simulate or run formal engine Repetitions and delays Assertions and coverage Specify events on outputs Run-to-failure
Debugging Trace from simulation of integrated component Scenario for designer-level component Importtrace
Diver ingredients Waveform-based interface Formal analysis Interactive define/run/view Event-guided test cases Climate for DLV simulation
What activities does DLV include? Debugging Lightweight verification Observation Checking assertions and coverage points Bug hunting Exploring corner cases Observing mainstream behavior
Conclusions DLV activity should scale linearly with the amount of effort spent Recommended recipe: • Waveform-based interface • Interactive define/run/view • Integration with common tools • Driving inputs • Simulation • Event-based test cases • A touch of formal analysis