Lab 3

1. Lab 3 Jorge Crichigno

2. Half-adder

3. Half-adder Testbench

4. Waveform for half-adder simulation tb stimulus 0 0 1 0 1 0 0 1 0 0 0 0 10 ns testbench ha x x_signal s s_signal y c y_signal c_signal

5. Full-adder

6. Full-adder Testbench

7. Waveform for full-adder simulation tb testbench fa x x_signal s s_signal y c y_signal c_signal z z_signal

8. Lab 3 - Sequential Statements • Process. Type of processes. Process with sensitivity list. Process with wait statement. Example. • Sequential Signal Assignment Statement. Syntax. Examples. Pitfall. Intermediate value. Conceptual implementation • Variables. Syntax. Intermediate value. Example. Conceptual implementation • Case statement. Syntax. Example. Multiplexor. Conceptual implementation.

9. Lab 3 - Sequential Statements Process • Contains a set of sequential statements to be executed sequentially • The whole process is a concurrent statement • Can be interpreted as a circuit part enclosed inside of a black box • Two types: with sensitive list and with wait statement

10. Lab 3 - Sequential Statements A process with a sensitivity list • Syntax process (sensitivity_list) declarations; begin sequential statement; sequential statement; . . . end process;

11. Lab 3 - Sequential Statements Process with sensitivity list. Interpretation: “black box, indivisible circuit part”. Sensitivity list Note: The execution of the process is initiated whenever an event occurs on any of the signals in the sensitivity list For practical purposes, you can regards a process as a “big” concurrent signal assignment statement

12. Waveform for Example 1 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 Process not activated on B change

13. A Process With wait Statement • Process has no sensitivity list • Process continues the execution until a wait statement is reached and then suspended • Forms of wait statement: • waiton signals; • waituntil boolean_expression; • waitfor time_expression;

14. Sequential Signal Assignment Statement Syntax: Signal_name <= value_expression; undefined 0 0 1 0 1 1 1 0 0 1 1 0 0 1 0 1 U U U U 0 0 0 1

15. Sequential Signal Assignment Statement If all assignments are within DELTA-delay, only the last assignment takes effect. You can think as the signals are not updated until the end of the process (i.e., it never assumes any “intermediate” value).

16. Variable Assignment Statement Syntax: Variable_name := value_expression; Used inside processes. The assignment takes effect “immediately”. Note: Easy to understand, but not clear hardware mapping!Use signal always you can; rely on variables only for the characteristics that cannot be described by signals Conceptual implementation

17. Case Statement Syntax: Example:

18. Example of case statement: Multiplexor Introduction to Multiplexers Truth Table

19. 4-to-1 multiplexer – VHDL Implementation Architecture ARCHITECTURE multiplexor4x1 OF mux4x1 IS BEGIN PROCESS(S, D0, D1, D2, D3) BEGIN CASE S IS WHEN "00"=> Y <= D0; WHEN "01"=> Y <= D1; WHEN "10“=> Y <= D2; WHEN OTHERS => Y <= D3; END CASE; END PROCESS; END multiplexor4x1; Entity ENTITY mux4x1 IS PORT ( S : IN STD_LOGIC_VECTOR (1 downto 0); D0 : IN STD_LOGIC; D1 : IN STD_LOGIC; D2 : IN STD_LOGIC; D3 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mux4x1;