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Explore the design and synthesis of Finite State Machines (FSMs) using Moore and Mealy models. Learn about state transitions, outputs, optimization, and VHDL implementation nuances.
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Finite State Machines Mixed Style RTL Modeling Extraído da George Mason Univ.ECE 545Lecture 5 MC 603/613 - 2006 1 - 1
Finite State Machines (FSMs) • Any Circuit with Memory Is a Finite State Machine • Even computers can be viewed as huge FSMs • Design of FSMs Involves • Defining states • Defining transitions between states • Optimization / minimization • Above Approach Is Practical for Small FSMs Only MC 603/613 - 2006 1 - 2
X X Y CC CC FF FF Si+1 Si Y CC Si+1 Si Máquina de Estados Circuito Sequencial Síncrono Genérico Máquina de Moore Máquina de Mealy Saída Y pode mudar emqualquer instante, em função da entrada X Saída Y muda apenas na transição do clock MC 603/613 - 2006 1 - 3
S0 S3 S1 S2 Síntese de uma máquina de estados Mealyentr / saída Mooreentr Tabela de Transição de Estados Diagrama de Transição de Estados MC 603/613 - 2006 1 - 4
Síntese de uma máquina de estados • Codificação dos estados • S0 = 00 etc • Equações booleanas dos circuitos combinacionais • Si+1 = fS (Si, X) • Y = fY (Si, X) (em maq. de Moore, só S) • Sintetizar os CCs • Elementos de memória podem ser FF-D ou FF-JK MC 603/613 - 2006 1 - 5
Moore FSM • Output Is a Function of Present State Only Inputs Next State function Next State Present State Present StateRegister clock reset Output function Outputs MC 603/613 - 2006 1 - 6
Mealy FSM • Output Is a Function of a Present State and Inputs Inputs Next State function Next State Present State Present StateRegister clock reset Output function Outputs MC 603/613 - 2006 1 - 7
Moore Machine transition condition 1 state 2 / output 2 state 1 / output 1 transition condition 2 MC 603/613 - 2006 1 - 8
Mealy Machine transition condition 1 / output 1 state 2 state 1 transition condition 2 / output 2 MC 603/613 - 2006 1 - 9
Moore vs. Mealy FSM (1) • Moore and Mealy FSMs Can Be Functionally Equivalent • Equivalent Mealy FSM can be derived from Moore FSM and vice versa • Mealy FSM Has Richer Description and Usually Requires Smaller Number of States • Smaller circuit area MC 603/613 - 2006 1 - 10
Moore vs. Mealy FSM (2) • Mealy FSM Computes Outputs as soon as Inputs Change • Mealy FSM responds one clock cycle sooner than equivalent Moore FSM • Moore FSM Has No Combinational Path Between Inputs and Outputs • Moore FSM is more likely to have a shorter critical path MC 603/613 - 2006 1 - 11
0 1 0 S0 / 0 1 S1 / 0 S2 / 1 1 0 Moore FSM - Example 1 • Moore FSM that Recognizes Sequence “10” reset S0: No elements of the sequence observed S2: “10” observed S1: “1” observed Meaning of states: MC 603/613 - 2006 1 - 12
Mealy FSM - Example 1 • Mealy FSM that Recognizes Sequence “10” 0 / 0 1 / 0 1 / 0 S0 S1 reset 0 / 1 S0: No elements of the sequence observed S1: “1” observed Meaning of states: MC 603/613 - 2006 1 - 13
Moore & Mealy FSMs – Example 1 clock 0 1 0 0 0 input S0 S1 S2 S0 S0 Moore S0 S1 S0 S0 S0 Mealy MC 603/613 - 2006 1 - 14
FSMs in VHDL • Finite State Machines Can Be Easily Described With Processes • Synthesis Tools Understand FSM Description If Certain Rules Are Followed • State transitions should be described in a process sensitive to clock and asynchronous reset signals only • Outputs described as concurrent statements outside the process MC 603/613 - 2006 1 - 15
Moore FSM process(clock, reset) Inputs Next State function Next State Present StateRegister clock Present State reset concurrent statements Output function Outputs MC 603/613 - 2006 1 - 16
Mealy FSM process(clock, reset) Inputs Next State function Next State Present State Present StateRegister clock reset Output function Outputs concurrent statements MC 603/613 - 2006 1 - 17
FSM States (1) architecture behavior of FSM is type state is (list of states); signal FSM_state:state; begin process(clk, reset) begin if reset = ‘1’ then FSM_state <= initial state; elsif (clock = ‘1’ and clock’event) then case FSM_state is MC 603/613 - 2006 1 - 18
FSM States (2) case FSM_state is when state_1 => if transition condition 1 then FSM_state <= state_1; end if; when state_2 => if transition condition 2 then FSM_state <= state_2; end if; end case; end if; end process; MC 603/613 - 2006 1 - 19
0 1 0 S0 / 0 1 S1 / 0 S2 / 1 1 0 Moore FSM - Example 1 • Moore FSM that Recognizes Sequence “10” reset MC 603/613 - 2006 1 - 20
Moore FSM in VHDL (1) TYPE state IS (S0, S1, S2); SIGNAL Moore_state: state; U_Moore: PROCESS (clock, reset) BEGIN IF(reset = ‘1’) THEN Moore_state <= S0; ELSIF (clock = ‘1’ AND clock’event) THEN CASE Moore_state IS WHEN S0 => IF input = ‘1’ THEN Moore_state <= S1; ELSE Moore_state <= S0; END IF; MC 603/613 - 2006 1 - 21
Moore FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Moore_state <= S2; ELSE Moore_state <= S1; END IF; WHEN S2 => IF input = ‘0’ THEN Moore_state <= S0; ELSE Moore_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN Moore_state = S2 ELSE ‘0’; MC 603/613 - 2006 1 - 22
Mealy FSM - Example 1 • Mealy FSM that Recognizes Sequence “10” 0 / 0 1 / 0 1 / 0 S0 S1 reset 0 / 1 MC 603/613 - 2006 1 - 23
Mealy FSM in VHDL (1) • TYPE state IS (S0, S1); • SIGNAL Mealy_state: state; • U_Mealy: PROCESS(clock, reset) • BEGIN • IF(reset = ‘1’) THEN • Mealy_state <= S0; • ELSIF (clock = ‘1’ AND clock’event) THEN • CASE Mealy_state IS • WHEN S0 => • IF input = ‘1’ THEN • Mealy_state <= S1; • ELSE • Mealy_state <= S0; • END IF; MC 603/613 - 2006 1 - 24
Mealy FSM in VHDL (2) WHEN S1 => IF input = ‘0’ THEN Mealy_state <= S0; ELSE Mealy_state <= S1; END IF; END CASE; END IF; END PROCESS; Output <= ‘1’ WHEN (Mealy_state = S1 AND input = ‘0’) ELSE ‘0’; MC 603/613 - 2006 1 - 25
resetn w = 1 ¤ ¤ A z = 0 B z = 0 w = 0 w = 0 w = 1 w = 0 ¤ C z = 1 w = 1 Moore FSM – Example 2: State diagram MC 603/613 - 2006 1 - 26
Next state Present Output z state w = 0 w = 1 A A B 0 B A C 0 C A C 1 Moore FSM – Example 2: State table MC 603/613 - 2006 1 - 27
Moore FSM process(clock, reset) Input: w Next State function Next State Present StateRegister Present State: y clock resetn concurrent statements Output: z Output function MC 603/613 - 2006 1 - 28
Moore FSM – Example 2: VHDL code (1) USE ieee.std_logic_1164.all ; ENTITY simple IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END simple ; ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN MC 603/613 - 2006 1 - 29
Moore FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; WHEN C => IF w = '0' THEN y <= A ; ELSE y <= C ; END IF ; END CASE ; MC 603/613 - 2006 1 - 30
Moore FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; z <= '1' WHEN y = C ELSE '0' ; END Behavior ; MC 603/613 - 2006 1 - 31
Moore FSM process (w, y_present) Input: w Next State function Next State: y_next process (clock, resetn) Present StateRegister Present State: y_present clock resetn concurrent statements Output: z Output function MC 603/613 - 2006 1 - 32
Alternative VHDL code (1) ARCHITECTURE Behavior OF simple IS TYPE State_type IS (A, B, C) ; SIGNAL y_present, y_next : State_type ; BEGIN PROCESS ( w, y_present ) BEGIN CASE y_present IS WHEN A => IF w = '0' THEN y_next <= A ; ELSE y_next <= B ; END IF ; WHEN B => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; MC 603/613 - 2006 1 - 33
Alternative VHDL code (2) WHEN C => IF w = '0' THEN y_next <= A ; ELSE y_next <= C ; END IF ; END CASE ; END PROCESS ; PROCESS (clock, resetn) BEGIN IF resetn = '0' THEN y_present <= A ; ELSIF (clock'EVENT AND clock = '1') THEN y_present <= y_next ; END IF ; END PROCESS ; z <= '1' WHEN y_present = C ELSE '0' ; END Behavior ; MC 603/613 - 2006 1 - 34
resetn ¤ w = 1 z = 0 ¤ ¤ w = 0 z = 0 w = 1 z = 1 A B ¤ w = 0 z = 0 Mealy FSM – Example 2: State diagram MC 603/613 - 2006 1 - 35
z Next state Output Present state w = 0 w = 1 w = 0 w = 1 A A B 0 0 B A B 0 1 Mealy FSM – Example 2: State table MC 603/613 - 2006 1 - 36
Mealy FSM process(clock, reset) Input: w Next State function Next State Present State: y Present StateRegister clock resetn Output: z Output function concurrent statements MC 603/613 - 2006 1 - 37
Mealy FSM – Example 2: VHDL code (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Mealy IS PORT ( clock : IN STD_LOGIC ; resetn : IN STD_LOGIC ; w : IN STD_LOGIC ; z : OUT STD_LOGIC ) ; END Mealy ; ARCHITECTURE Behavior OF Mealy IS TYPE State_type IS (A, B) ; SIGNAL y : State_type ; BEGIN PROCESS ( resetn, clock ) BEGIN IF resetn = '0' THEN y <= A ; ELSIF (clock'EVENT AND clock = '1') THEN MC 603/613 - 2006 1 - 38
Mealy FSM – Example 2: VHDL code (2) CASE y IS WHEN A => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; WHEN B => IF w = '0' THEN y <= A ; ELSE y <= B ; END IF ; END CASE ; MC 603/613 - 2006 1 - 39
Mealy FSM – Example 2: VHDL code (3) END IF ; END PROCESS ; WITH y SELECT z <= w WHEN B, z <= ‘0’ WHEN others; END Behavior ; MC 603/613 - 2006 1 - 40