Review: Delay Definitions

1. Propagation delay tp = (tpHL + tpLH)/2 50% tpHL tpLH 90% signal slopes 50% 10% tf tr Review: Delay Definitions Vin Vout Vin input waveform t Vout output waveform t

2. CMOS Inverter: Dynamic • Transient, or dynamic, response determines the maximum speed at which a device can be operated. VDD Vout = 0 CL tpHL = f(Rn, CL) Rn Vin = V DD

3. CG4 M2 M4 CDB2 Vout Vout2 Vin CGD12 CDB1 M3 M1 CG3 Sources of Capacitance Vout Vin Vout2 CL Cw intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance

4. MOS Intrinsic Capacitances • Structure capacitances • Channel capacitances • Depletion regions of the reverse-biased pn-junctions of the drain and source

5. Transistor Capacitance Values for 0.25 Example: For an NMOS with L = 0.06 m, W = 0.36 m, LD = LS = 0.625 m CGSO = CGDO = Cox xd W = Co W = 0.11 fF CGC = Cox WL = 0.52 fF so Cgate_cap = CoxWL + 2CoW = 0.74 fF Cbp = Cj LS W= 0.45 fF Csw = Cjsw (2LS + W) = 0.45 fF so Cdiffusion_cap = 0.90 fF

6. CDB2 CDB1 Review: Sources of Capacitance Vout Vin Vout2 CL CG4 M2 M4 CGD12 Vout Vout2 pdrain Vin ndrain Cw M3 M1 CG3 intrinsic MOS transistor capacitances extrinsic MOS transistor (fanout) capacitances wiring (interconnect) capacitance

7. Vout V 2CGB1 V V CGD1 Vout M1 Vin Vin V M1 Gate-Drain Capacitance: The Miller Effect • M1 and M2 are either in cut-off or in saturation. • The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor). • A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value

8. Extrinsic (Fan-Out) Capacitance • The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4. Cfan-out = Cgate (NMOS) + Cgate (PMOS) = (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox) • Simplification of the actual situation • Assumes all the components of Cgate are between Vout and GND (or VDD) • Assumes the channel capacitances of the loading gates are constant

9. Components of CL (0.25 m)

10. Wiring Capacitance • The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. • Wiring capacitance is growing in importance with the scaling of technology.

11. Parallel Plate Wiring Capacitance current flow L electrical field lines W H tdi dielectric (SiO2) substrate permittivity constant (SiO2= 3.9) Cpp = (di/tdi) WL

12. Permittivity Values of Some Dielectrics

13. Sources of Interwire Capacitance Cwire = Cpp+ Cfringe+ Cinterwire = (di/tdi)WL + (2di)/log(tdi/H) + (di/tdi)HL fringe interwire pp

14. Impact of Fringe Capacitance H/tdi = 1 H/tdi = 0.5 Cpp W/tdi

15. Impact of Interwire Capacitance

16. Insights • For W/H < 1.5, the fringe component dominates the parallel-plate component. Fringing capacitance can increase the overall capacitance by a factor of 10 or more. • When W < 1.75H interwire capacitance starts to dominate • Interwire capacitance is more pronounced for wires in the higher interconnect layers (further from the substrate) • Rules of thumb • Never run wires in diffusion • Use poly only for short runs • Shorter wires – lower R and C • Thinner wires – lower C but higher R • Wire delay nearly proportional to L2

17. Wiring Capacitances pp in aF/m2 fringe in aF/m per unit wire length in aF/m for minimally-spaced wires

18. Dealing with Capacitance • Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO2 • family of materials that are low-k dielectrics • must also be suitable thermally and mechanically and • compatible with (copper) interconnect • Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance • SOI (silicon on insulator) to reduce junction capacitance