Class Presentation for Advanced VLSI Course Presented by: Behzad Eghbalkhah

1. Class Presentation for Advanced VLSI Course Presented by:Behzad Eghbalkhah Major Reference is: Mixed Body-Bias Techniques with Fixed Vt and Ids Generation Circuits Masaya Sumita, Shiro Sakiyama, Masayoshi Kinoshita, Yuta Araki,Yuichiro Ikeda, Kouhei Fukuoka Matsushita Electric Industrial, Nagaokakyo, Japan In ISSCC2004 Presentation Date: Dec.2004

2. OUTLINE • Design Challenges of sub-1V CMOS • Proposed Body-Bias Techniques • Experimental Results • Body-Bias Generator • SRAM • Register File • Conclusion and Summary

3. Design Challenges of sub-1V CMOS • Managing all circuit categories to meet the required yield is a complex problem. • Two important problems to be addressed: • Reversal Phenomenon of the speed variation at the high-low temperature. • Lower limit of write noise margin of SRAM (WNM)

4. Effect of Ids on Circuit Delay • Circuit Delay Which temperature, which critical path is a worst delay? • Need to test at all temperature Huge test cost !!! Fixed Ids will improve Delay Sensitivity.

5. Effect of Vt on the WNM of SRAM • Noise Margin of SRAM W.N.M is critical at the lower temperature and voltage. Fixed Vt will improve N.M sensitivity Simulation Results

6. Proposed Body-Bias Techniques • Goals Improving N.M sensitivity and circuit delay. • Strategy Control Body-Bias to keep Ids or Vt fixed, regardless of temp. and process variation.

7. Body-Bias Generator System • FVtBBG VgsDesired Vt • FIdsBBG VgsVDD1(NMOS) VSS (PMOS)

8. Experimental Results • Dispersion 5 wafers with > 10% Vt variation. • Vb Correlation error : Fixed vs. External • ±30mV Vb error 3% Ids, 2% Vt variation Vb Errors are insignificant

9. Experimental Results • Vb for Fixed Vt Body-Bias Generation Stable body bias current can be maintained. • Vb for Fixed Ids Body-Bias Generation The negative temp. dependence of mobility narrows the adjustment range for Vb.

10. Experimental Results Fixed Vt vs. No Body-Bias • SRAM • At low temperature and Vtn/Vtp= High/Low wafer, the lower limit voltage is improved by 100mV. This results in approximately 26% reduction in power consumption. • At high temperature and Vtn/Vtp=Low/Low wafer, the active current is decreased by 75%. In other words, with SRAM, the FVtBBG is very effective for reducing power consumption.

11. Experimental Results • Register File (RF) Mixed Body-Bias Results • At VDD1=0.8V, speed reversal is improved and the delay variation is reduced by 85%. • In addition, the operating current is reduced by 15% at 100MHz and 125ºC.

12. Effect of each Body-Bias Scheme

13. Summary • Proposed Mixed Body Bias Techniques to fixed with Ids or Vt for each circuit . • Fixed Ids and Fixed Vt Body Bias Generator - Error of Correlation: ±30mV • SRAM using Fixed Vt Body Bias - Operation Voltage improved by 0.1V at low temperature. - Power reduced by 75% at high temperature. • Register File using Mixed Body Bias - Delay dependence on temperature is improved: positive slope - Delay variation is reduced by 85%. - Active current decreased by 15% at high temperature. • Mixed Body Bias Technique is very effective for mobile processor design!

14. References [1] M. Sumita et al., “Mixed Body-Bias Techniques with Fixed Vt and IdsGeneration Circuits,” ISSCC Feb. 2004. [2] J. Tschanz et al., “Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variation on Microprocessor Frequency and Leakage,” ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2002. [3] K. Kanda et al, “Design Impact of Positive Temperature Tependence on Drain Current in Sub-1V CMOS VLSIs,” IEEE J. Solid-State Circuits, vol. 36, pp. 1559-1564, Oct. 2001. [4] T. Douseki et al., “Static-Noise Margin Analysis for a Scaled-Down CMOS Memory Cell,” Journal of IEICE, vol. J75-C-2, no.7, pp. 350-361, Jul. 1992. [5] T. Douseki et al., “Static-Noise Margin Analysis of MOS SRAM Cells ,” Journal of IEEE Solid-State Circuits, vol. SC-22, no.5, Oct. 1987.