1 / 17

CPU Analysis & Review: Pipelining, Long & Short Bubbles, Branches, Efficiency

This lecture review on CPU analysis covers topics such as pipelining, long and short bubbles, branches, and efficiency. It also includes an overview of CPU history and evolution, as well as the Intel 8080 and its comparison to a breadboard setup.

batiste
Download Presentation

CPU Analysis & Review: Pipelining, Long & Short Bubbles, Branches, Efficiency

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ITEC 352 Lecture 23 CPU analysis

  2. Review • Pipelining • Long • Short • Bubbles • Branches • Efficiency

  3. Outline • CPU • History • Evolution

  4. Intel 8080 • 40 pins • How does this compare w/ your breadboard? • 7 registers • 78 instructions • 65,536 bytes of addressable memory • Programmable stacks As described in the manual

  5. Registers • A-H or 0-7 • A was the accumulator (where results were stored) • Pairs • Some instructions required certain registers to be used • I.e. B and C would be used for a certain instruction • Has a PSW (1 byte) in register A that stores the state of the machine

  6. Memory • 64k possible memory (2^16) • 8 bit cpu (no direct way to handle 16 bits) • Stack pointer • Programmer maintained • Instruction augmented • Program counter • 16 bits to tell CPU where to get next instruction • Instructions could be 1,2, or 3 bytes • Cautions against storing data and instructions together

  7. Addressing • Direct • Uses a register • Immediate • Instruction then address in memory • Stack • Convention for first / second places to get memory (pairs)

  8. Assembly • Style • Label Code Operand ;Comment • Data • Hex, Binary, Octal • Instructions • +,-,*,mod,and,or,not,shr,shl,xor • mvi register address • jmp address All arithmetic operations assume 2s complement format

  9. Assembly(2) • DW,DB,DS • Define a place in memory • MOV, LDAX, STAX (Load/Store register A) • CMP = Compare register / memory w/ register A • DAD • The double add (16 bit on an 8 bit) • Many others, but same complexity level

  10. Stack • push registerPair • pop registerPair • inx register (increment pointer) Put / Store registers / memory

  11. Capabilities? • What can a 2 Mhz CPU do? Not an intel CPU. However 1.76Mhz and ~15 MMapped registers

  12. GFX

  13. Pentium 1

  14. Pentium 3 P3

  15. i7 CPU

  16. Takeaway • CPU development is amazing • Double edged sword • When and why to goto low level

  17. Summary • CPU

More Related