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July , 2006

Network Security Processor and the Related SOC Design and Test Technologies Bist for RAm IN Seconds. July , 2006. Design (Layout). Defect Injection. Faulty Cell Behavior. Fault Models. Fault Models. Test Algorithms. Built-In Self-Test. Built-In Self-Repair. Tester.

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July , 2006

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  1. Network Security Processor and the Related SOC Design and Test TechnologiesBist for RAm IN Seconds July , 2006

  2. Design (Layout) Defect Injection Faulty Cell Behavior Fault Models Fault Models Test Algorithms Built-In Self-Test Built-In Self-Repair Tester Memory Testing Problem & Solutions • Problem: memory manufacturing is not perfect • Need testing, diagnosis, and repair • RAMSES: RAM/Flash fault simulator • TAGS: RAM/Flash test algorithm (pattern) generator • BRAINS: RAM BIST generator • FAME: memory failure analyzer

  3. gbrains GUI Memory Compiler IP Generators Command Scripts Memory Library BID Constructor BIST Memory Spec Test Requirement Intermediate Description BIST Templates Compiler Kernel BRAINS BIST Design Activation Sequences Integration Scripts BRAINS: BIST for RAMs in Seconds Simulation/Synthesis/P&R Flow Memory BIST Automation Flow

  4. Read port Write port Read-write port Group 0 Group 1 Single-port Controller Sequencer 0 SRAM Dual-port SRAM 2R1W Register File Group 0 Single-port Sequencer 1 SRAM Test Schedule and Test Grouping Parameters: Memory type Memory spec. Power constraint User define

  5. Algorithm Programming & Test Scheduling

  6. Driving Capability & Pipeline Optimization

  7. BIST Circuit Generation Flow Start BID Memory model, address, word width Memory Info. Default / Programmable Test Algorithm Test Scheduling Auto / User defined Driving/Timing Spec. Pin loading, latency BIST Compile RTL, TB, Syn. Script

  8. External Tester Memory BIST MBS MSI MBO MRD MSO MBC MBR MCK Controller Sequencer Sequencer Sequencer TPG TPG TPG TPG TPG TPG RAM RAM RAM RAM RAM RAM BIST Architecture

  9. Experiment Result & Comparison • Memory Spec: • 64 X 64: 2 modules • 64 X 128: 3 modules • 512 X 64: 1 module • 512 X 128: 2 modules • Full speed testing -- clock rate: 100 MHz • Diagnosis function • Test algorithm: March C- (Mentor), March CW (BRAINS)

  10. FAME • FAME: Failure Analyzer for Memories • MECA: Memory Error Catcher and Analyzer • RAMSES: RAM fault simulator • TAGS: RAM test algorithm generator • ERA: RAM error analyzer • MDD: Memory Defect Diagnosis Tool • AFA: Automatic Fault Analyzer • FPA: Failure/Fault Pattern Analyzer • GUI-based Failure/Fault Pattern Viewer

  11. FAME: Failure Analyzer for Memory

  12. Realistic Defect Injection • Purpose: to determine if a circuit is damaged by a certain defect Contact/Via Missing Contact Short Defects D Open Defects D

  13. Fault Patterns Defective Netlist Reduction Simulation Prediction Stage Application Stage Defect Dictionary Realistic Fault Patterns Defect Candidates Diagnostics Using Fault Patterns • A cause-effect approach:

  14. Fault Pattern Analysis Results

  15. Memory Defect Diagnostics (MDD) Memory Defect Diagnostics

  16. Failure/Fault Pattern Viewer

  17. Summary • Fault-pattern oriented methodology for defect diagnostics • Layout-based defect injection and defect dictionary creation • Combines strengths of conventional failure-pattern approach and our fault-type approach • Integrated memory failure analysis framework • Cost-effective defect identification and yield improvement • BRAINS creates BIST circuit for all memory cores • Used in early stage of SOC design • Memory library provides easy access to different memory types

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