1 / 26

Bolstering Faith in GasP Circuits through Formal Verification

Bolstering Faith in GasP Circuits through Formal Verification. Xiaohua Kong, Radu Negulescu McGill University. State conductor. State conductor. s. t. r0. r1. r2. Cell 0. Cell 1. Cell 2. Cell 3. r. y. y. rr0. E 0 , 2. rr1. rr2. rr3. c. r1. r0. F 0, 4. d. Bin. Bout.

bbeth
Download Presentation

Bolstering Faith in GasP Circuits through Formal Verification

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Bolstering Faith in GasP Circuitsthrough Formal Verification Xiaohua Kong, Radu Negulescu McGill University

  2. State conductor State conductor s t r0 r1 r2 Cell0 Cell1 Cell2 Cell3 r y y rr0 E0, 2 rr1 rr2 rr3 c r1 r0 F0, 4 d Bin Bout Cell4 Cell5 Cell6 Cell7 d1 d2 d3 d4 a a b d5 d6 d7 d8 x Cell8 Cell9 Cell10 Cell11 Control Unit0 Control Unit1 E1, 2 Ebergen 2001 Brunvand 1995 V rr0 rr1 d9 d10 d11 d12 cc F1, 4 Cell12 Cell13 Cell14 Cell15 rr13 rr14 rr15 rr16 d1 r14 r15 r16 Hierarchy System-Level Cell-Level Unit-level Switch-Level

  3. Signal-Level Specification Levels of Verification GasP FIFO System-Level Specification GasP Cells Cell-Level Specification GasP Units Switch-Level Implementation Switch-Level Model

  4. Outline • Preliminaries • Process spaces • Active-edge specification • Specification Construction • Signal-level specification • System-level specifications • Hierarchical Verification • Conclusion

  5. c g a b C c a,b c r e g e a,b,c a a,b,c b g c Process Spaces a c b C-element a b c (b) Waveform

  6. Process Spaces (cont’d) • Product (Parallel Composition ) • Refinement • Relabeling • Semi-hiding

  7. Ar A a Ar Ar 0 3 6 9 0 2 A B B r Br 1 4 7 10 Aa Ar A a Ar Aa Ar Br Ba 12 15 18 21 24 4 5 1 3 2 5 8 11 B r Ba Ba 13 16 19 22 25 Ba 27 Br 0 3 6 9 0 1 6 Ar , Aa 14 17 20 23 26 B r Ba Br Ba 1 4 7 10 28 2 7 2 29 Active-Edge Specification

  8. Criteria of Good Specifications • Simple, simple and simple • Simple so it is easy to construct • Simple so it is easy to understand • Simple so it is easy to compute • Simple so it is easy to reuse

  9. R0 R1 A0 A1 V V 8 0 1 V A0 R0 R0 V A1 A1 A1 To state2 5 6 7 A0 V A1 R1 A0 R0 R1 R1 R1 4 2 3 A0 R0 Active-edge Specification Construction R0 R1 Control Unit0 A0 A1 V

  10. 8 0 1 V Bin+ Bin To state2 Bout+ Bout+ Bout+ 5 6 7 Bin+ Bin Bout Bout Bout 4 2 3 Bin+ Bin Specification of GasP Units Bin Bout GasP Unit Bout+ Bin+ V

  11. 1 V0 V1 V2 V3 2 3 V4 V5 V6 V7 4 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 System-Level Specification Cell0 Cell1 Cell2 Cell3 Cell4 Cell5 Cell6 Cell7 Cell8 Cell9 Cell10 Cell11 Cell12 Cell13 Cell14 Cell15

  12. System-Level Specification (Cont’d) Capacity of 16 data items: 0 ≤ #V0 – #V19 ≤ 16 r0, rr0 r0, rr0 r0, rr0 r0, rr0 0 1 2 16 … g e e e r16, rr16 r16, rr16 r16, rr16 r16, rr16

  13. System-Level Specification (Cont’d) Data Movement on top row

  14. r2, rr2 V1 r1, rr1 r1, rr1 r3 d1 r1, rr1 r2, rr2 d2 d1 V4 V1 r1, rr1 d3 r1, rr1 (a) (b) (c) V1 r1, rr1 Top Row Rule Specification V0 V1 Cell0 V4

  15. GasP Units Signal-Level Specification Switch-Level Implementation Switch-Level Model Switch-level Verification GasP FIFO System-Level Specification GasP Cells Cell-Level Specification

  16. State conductor State conductor s t r y y c d Bin Bout a a b x Control Unit0 Control Unit1 V cc GasP Unit Implementation

  17. Specunit ? NodeBin  NodeBout  a  y  and  NandNode  r  s  t  d  c Switch-Level Modeling d c Node with Keeper Node with Keeper cout y NandOut y rout sout s r NodeBin NodeBout BinDn BoutDn BoutUp BinUp Nand Node NandUp t Bout a and a Bin aout NandDn Control Unit1 Control Unit0

  18. g g g BinDn BinUp g e g BinDn BinUp Bin Bin e g BinUp BinDn BinDn BinUp r BinUp, BinDn, Bin Node Models r NandDn NandUp g e r NandDn NandUp NandOut NandOut e g NandUp NandDn NandUp NandDn r NandUp, NandDn, NandOut

  19. GasP Cells Cell-Level Specification GasP Units Signal-Level Specification Cell-level Verification GasP FIFO System-Level Specification Switch-Level Implementation Switch-Level Model

  20. Cell-Level Verification v1 r0_Bout+ r1_Bin+ r1 a0 r1 r0 r1rr1_Bin+ b0 E0 F0 r0_Bout- r0 rr0 rr1 d1 rr1 rr0_Bout- Selection r0rr0 rr0 Selection r1rr1 d1_Bin+ F1 E1 d1 SpecCell1 ? r0rr0  r1rr1 d1

  21. GasP FIFO System-Level Specification GasP Cells Cell-Level Specification Cell-level Verification GasP Units Signal-Level Specification Switch-Level Implementation Switch-Level Model

  22. Table 1. Relative timing constraints for the linear GasP unit. Experimental Results [1] A keeper is used at Sun to guard against this noise sensitivity.

  23. r0 r1 r2 rr0 rr1 rr2 rr3 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 rr13 rr14 rr15 rr16 r14 r15 r16 Square FIFO [Ebergen 01]

  24. Top Row Simplified 1 V0 V2 V1 V3 V4 V5 V6 V7 d5 d6 d7 d8 d9 d10 d11 d12 rr13 rr14 rr15 rr16 r14 r15 r16

  25. 16 15 14 13 11 10 9 7 6 5 Where is Stubborn Donkey ? V0 V2 V1 V3 V4 V5 V6 V7 12 d5 d6 d7 d8 8 d9 d10 d11 d12 rr13 rr14 rr15 rr16 4 3 2 1 r14 r15 r16

  26. Conclusion • Specification and Verification of GasP • Modularity of GasP leads to simple specs • Simple system level specifications • Simple active-edge unit specs

More Related