Spur Reduction Techniques in Direct Digital Synthesizers

1. Spur Reduction Techniques in Direct Digital Synthesizers • Introduction/Review of DDS’s • Theory of Spur Generation • Spur Reduction Techniques • Spurless Fractional Divider • Wheately Jitter Injection DDS • Randomized DAC DDS • Nonuniform Clock DDS • Nicholas & Samueli Technique (Will Not Be Discussed in Paper)

2. Direct Digital Synthesizers • DDSs also called Numerically Controlled Oscillators • Directly Synthesize a Selectable Output Frequency from a Clock Using Digital Techniques • Types of DDSs • Pulse Output • Sine Output • Fractional Divider • Phase Interpolation • Other

3. Pulse Output DDS f=2pr r Frequency Word K Clock Frequency=fc 6p 3rd Carry N-Bit Accumulator (Register Value = R) 4p 2nd Carry Fo Carry=Pulse Output fo dt dr or df 2p 1st Carry • Each Cycle R + K R Mod 2N • r + Fo r • Average Output Frequency: fo=Fo fc • Fractional Frequency Word: Fo=K/2N • Fractional Register: Fract(r)=R/2N Clock Cycles 0 0 1 2 3 4 5 6 7 Pulse Output

4. Typical Pulse Output DDSFrequency Spectrum • Large Spurs Very Close to Carrier • Nature of Spurs Changes Drastically with Fo • Filtering Doesn’t Necessarily Reduce Phase Jitter

5. Clock Freq=fc Frequency Word K N-Bit Accumulator Angle W Bits Sine Look-up Table • Output J Bits M-Bit DAC Stepped DDS Output Output fo Sine Output DDS Output Must be Filtered to Recover Pure Sine Wave

6. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 dBc Typical Sine Output DDSFrequency Spectrum 5-Bit DAC 11-Bit DAC fo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz

7. fc fo = n + Fo Fractional Divider or Pulse Swallowing DDS • Divider Normally ¸n • Each Divide Cycle Clocks Accumulator • R + K R Mod 2N • On Carry: ¸n+1 Next Divide Cycle • On Average: fo Divide by n/n+1 fc n/n+1 Control Carry Output N-Bit Accumulator K

8. Phase Interpolation DDS Linear Phase Detector fc R K DAC N-Bit Accumulator Loop Amp Carry Output n/n+1 Control VCO Divide by n/n+1 fo

9. t-Space Sampled Spectrum Output Spectrum r-Space Spectrum Harmonics 1 1 3 3 5 5 7 7 1 3 5 7 r-Space Frequency fo fo 2fc fo fc 2fc Spur Generation in DDSs Accumulator Samples v(r) at rn=fotn Stepped Output Hold Function Look-Up Table v(r) • Quantized Sine Wave (Sine DDS) • Square Wave (Pulse DDS) • v(r) Periodic in r (Period=1) • Discrete r-Space Harmonics • v(fot) Translates mth Harmonic to mfo • Sampling at tn Causes Aliasing at f=mfo - m’fc • Stepping Adds Hold-Function Filter • Spectrum of Hold Function Sinc2(pf/fc)

10. Spur Reduction Techniques Spurless Fractional Divider Wheately Jitter Injection Randomized DAC DDS Nonuniform Clock DDS Nicholas & Samueli Technique Totally Random Output Jitter Injection Jitter Injection Nonuniform Sampling Force K to be Odd Reducing Spurs in DDSs • Spurs Occur Because Uniformly Stepped Sequences Periodic (Period = N’tc) • Destroying Periodicity or Uniformity will Reduce Spurs

11. Spurless Fractional Divider • Each Output Clock Random N-Bit Word Pn Generated • Pn= 0 to 2N-1 • If Pn < K then Divide by n+1 • Fo = Probability that Pn<K • On Average fo = fc/(n +Fo) • n/n+1 Sequence Totally Random so No Spurs Generated • Produces White Frequency Jitter • Sf(f) Proportional to 1/f2 Clock Period = tc Output Period = to Divide by n/n+1 n/n+1 Control Pn< K N-Bit Word Comparator K Pn Random Number Generator

12. Wheatley Jitter Injection DDS • Adds Random Pn to R Before Carry • r Jittered from 0 to Fo • Equivalent to White Phase Jitter • Washes Out Spurs • Produces White Phase Noise Clock Freq=fc Frequency Word K N-Bit Accumulator (Register Value = R) Random Number Generator R N-Bit Adder Pn = 0 to K-1 Carry ¸2 Fo=K/2N “Square” Wave Output fo

13. Wheatley Simulation Results Without Jitter Injection With Jitter Injection

14. Heuristic Explanation Spur Height Reduced if Jitter Large Enough Sf(f) Jitters Output at fo by sf Jitters spur from mth Harmonic of v(r) by msf fo fspur f Produces Broadband Spectrum Destroying Coherence With Register Jitter Register to Voltage Conversion v(r) rn=Fract(nFo) v(rn + pn) rn + pn N-Bit Accumulator S Random Number Generator pn Fractional Frequency Fo

15. Randomized DAC DDS • Sine Output Embodiment • Can be Inserted into Existing Sine Output DDSs • Can Also be Used in Phase Interpolation DDS • Washes Out Spurs • Produces Much Lower Level of White Phase Noise Clock Freq=fc Frequency Word K Sine Look-up Table Output J Bits N-Bit Accumulator R Random Number Generator kn = 0 to K’-1 J-Bit Adder K’=2J-M M-Bit DAC Output fo

16. 0 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 dBc dBc Randomized DAC DDS Experimental Results 5-Bit DAC No Jitter 5-Bit DAC With Jitter 11-Bit DAC No Jitter fo=333.25 KHz fc=1 MHz Span=10 KHz RBW=10 Hz

17. Dt varies Pseudorandomly from 0 to 2tc Nonuniform Clock DDS K Odd Clock DR=KDt DR Calculator N-Bit Accumulator Ping Pong Switch DAC Dt Sine Look-up Table Pseudorandomly Non-uniform Clock Generator DAC Odd/Even Buffers Output Even Clock Odd Clock Even Clock

18. Conclusions • Randomization Techniques are an Effective Way of Reducing Spurs • Of Spur Reduction Methods Discussed • Jitter Injection Best Over-all Method • Produces Manageable Phase Noise • Minimimizes Added Complexity • Wheatley for Pulse Output • Randomized DAC for Sine Output & Phase Interpolation • Can Make Up for Technology Limitations