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ACA2008 HW3. Simplescalar: Victim Cache. 林仲祥 , 李苡嬋 CSIE, NTU 11 / 03, 2008. ISCA’90 (Norman P. Jouppi) “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers”. Victim Cache. 2. Victim Cache. General cache. data. Data. Hit.
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ACA2008 HW3 Simplescalar: Victim Cache 林仲祥, 李苡嬋CSIE, NTU11 / 03, 2008
ISCA’90 (Norman P. Jouppi) “Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers” Victim Cache 2
Victim Cache General cache data Data Hit data Miss Data Victim miss data data data Search data data data Victim cache Memory (or lower cache)
Victim Cache General cache data data Miss Data data Victim miss data data data Search data data data Victim cache Memory (or lower cache)
Victim Cache General cache data data Miss Data data Victim miss data data data Search data data LRU data data Victim cache Memory (or lower cache)
Victim Cache General cache data data Miss Data data Victim hit data data Search data data data Victim cache Memory (or lower cache)
HW3 How To Implement by SimpleScalar
Software Architecture • Cache cache.c / cache.h
Hardware Architecture • D-Cache L1 load store
sim-outorder.c • ruu_issue(); • for loads, first scan LSQ to see if a store forward is possible, if not, access the data cache. • ruu_commit(); • stores must retire their store value to the cache at commit. store load
cache.c • cache_create(); • create and initialize a general cache structure • cache_access(); • access a cache
cache.c: cache_create(); • Check all cache parameters • Allocate the cache structure • Initialize user parameters • Initialize cache stats • Allocate data blocks
cache.c: cache_access(); • Check for a hit • Fast hit • access to same block • Hit • access cache • update dirty (write hit) • update list by LRU policy • Miss • select the appropriate block to replace • write back replaced block data • read data block • update block tags • update dirty status (if cmd = write)
Other information… • Most modifications in this homework: • cache.c • cache.h • Cache configuration (refer to hack_guide.pdf) • <name>:<nsets>:<bsize>:<assoc>:<repl> • Ex. dl1:8:32:2:l • Name = dl1 • # of set = 8 • Block size = 32 bytes • # of way = 2 • Replacement policy = LRU # of set = 8 block size = 32 bytes # of way (assoc) = 2