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TransEDA Presentation

TransEDA Presentation. OCP-IP Meeting TI Nice June 2004. Company Overview. EDA company founded in 1990 in UK Focus on design verification

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TransEDA Presentation

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  1. TransEDA Presentation OCP-IP Meeting TI Nice June 2004

  2. Company Overview • EDA company founded in 1990 in UK • Focus on design verification • Code, specification, assertion and protocol coverage, rules checking, verification IP, test optimization, formal verification, static and dynamic assertion-based verification, transistor abstraction • Over 3500 licenses installed in more than 600 sites around the world • 65 employees worldwide, support centers in North America, Europe and Asia

  3. A new TransEDA Company • August 2003: • Merge of Valiosys EDA division with TransEDA • Valiosys Group created with two subsidiaries • Complementary people, tools and technologies EDA Branch Embedded Software Branch

  4. Our Strengths Expertise in SoC verification usingassertion-based, coverage and formal methods Coverage Technology Assertions Expertise Formal Engines Pioneer in coverage-driven verification Assertion-based verification expertise Powerful and deployable formal engines Protocol checking and modeling competence Multi-language (VHDL, Verilog, PSL, SystemVerilog, Temporal “e”, etc) Verification IP Language Independent Open and independent solutions with links to industry standard tools: simulators, emulators, debuggers, etc.

  5. New Dimensions in Coverage Code Coverage Spec Coverage Functional Coverage Protocol Coverage Test Suite Optimization Enhanced products with significant synergies to fulfill the vision and bring immediate value to customers VN-Spec VN-Check VN-Property Improve-HDL VN-Cover VN-CoverEmulator Improve-HPK Verification IPs VN-Optimize

  6. VN-Check – RTL Style Checker • Quick & easy RTL rule checking • Pre-defined rule sets • Configurable to create your own rule sets • Manage multi-site HDL development • VHDL, Verilog and SystemVerilog support • Enforce consistent naming conventions • Enforce corporation-specific complex coding rules

  7. VN-Cover / VN-Cover EmulatorCode Coverage • Industry leading metrics • Supports simulators from • Cadence, Mentor Graphics, (ModelTech) and Synopsys • Supports emulators from • Cadence, Mentor Graphics, Axis (Verisity) and Eve • Reduce simulation time • Focus on areas that need further attention • Improve productivity HDL Design Metrics selection Instrumented Design Logic Simulator / Emulator HistoryFile Results analysis

  8. What is Coverability? • “Coverability is a solution to guide the designer onto the shortest path to full coverage, isolating unreachable design parts and providing help to complete coverage” • Compelling questions: • Is an uncovered part of the design reachable? • If it is reachable, how can it be reached? • Update the test-based coverage results with the ones from Coverability Analysis to give a unified static/dynamic measurement • Ultimate goal: achieve100% coverage in shortest time

  9. Coverability Benefits • Refines coverage results accuracy • Enables verification engineers to focus on reachable code • Guides designer on how to increase coverage • Increasing complexity makes it more difficult to reach coverage targets with test-bench alone • Helps verification of re-used or third-party IPs • Complemented by static Linting Technology, checking coverability prior to simulation

  10. Coverability Analysis in Details • Uncovered branches are synthesized into assertions and fed to a formal engine • Fully automatic process • Globally on all uncovered branches • One by one on user-selected uncovered items • Simple, automatic and affordable • No formal knowledge is necessary • No extra model checker to buy

  11. Specification Coverage Specification Property/Assertion Checking Coverage not verified Specification Coverage Gap Simulation RTL Netlist Emulation Transistor Equivalence Checking • VN-Spec is the first commercial EDA solution that enables linking the implementation and verification flows to initial specifications • VN-Spec traces requirements to measure and report their coverage across design evolutions and verification to completion • VN-Spec also performs impact analysis on requirement changes, additions and deletions

  12. Example of VN-Spec Flow Specifications (Spec.doc) Test Plan (Validation.txt) Test benches (test_*.v) Implementation files (*.v) Test reports (test_*.txt) The test result is known for each specification requirement Each feature is at least covered by one test Each test planned have a test bench associated All the specs have been implemented Each test bench verifies identified functionalities All tests have completed OK A test status is known for each implemented requirement

  13. imPROVE-HDL Assertion Checking • A complementary technique to simulation • Static vs. dynamic - No test vectors needed • Allow detection of bugs that are hard to find with a simulator • Exhaustive formal computation - 100% functional coverage • Usable all along the design flow • In the specification phase by architects to understand and fix ambiguities in the written specification and to define the test plan • In the RTL design phase by design engineers to compute expected behaviors and to catch bugs quickly and easily • In verification phase by verification engineers to exhibit complex behaviors and to find remaining difficult bugs

  14. imPROVE-HDLAssertion Checking HPK Protocol Protocol Environment Automatically created Environment Constraints PSL, OVA, PEC, temporal-e, VHDL/Verilog RTL / Gate Model (VHDL / Verilog) Protocol Compliant IP (RTL VHDL or Verilog) Assertions PSL, OVA, PEC, temporal-e, VHDL/Verilog Protocol Properties Predefined in the HPK imPROVE-HDL Formal Property Checker imPROVE-HPK Hardware Protocol Kit Test sequence found: VCD or debugging tool Exhaustively verified

  15. imPROVE-HPKProtocol Checking • Automatic formal verification of blocks based on standard protocols • Automatically creates the environment and properties • Automatically verifies the properties and coverage scenarios • Automatically creates VCD output for debugging in case of violation • Supported protocols: OCP, AHB, PCI, PCIX (more to come) • Compliance and performance analysis properties • Easy-to-use and to deploy tool • User sets only design specific parameters • Automatically select to run the full protocol or select from available properties to create automatic script

  16. HPK OCP 1.0 Features Covered • 52 protocol properties, 12 performance properties, over 60 coverage scenarios • More than 70 configuration parameters • 100% of the protocol, including: • all OCP 1.0 parameters and signals • all control handshaking features • pipelined masters and slaves • incrementing and streaming bursts • complete multi-threading • all data handshaking features • control and status signals

  17. HPK OCP 2.0 Features Covered • 66 protocol properties, 8 performance properties, over 100 coverage scenarios • More than 110 configuration parameters • 100% of the protocol, including: • all OCP 2.0 parameters and signals • all control handshaking features • pipelined masters and slaves • incrementing, wrapping and streaming bursts; imprecise bursts • complete multi-threading • all data handshaking features (July 2004)

  18. HPK AHB Features Covered • 70 properties, 9 performance properties, over 200 coverage scenarios • More than 60 configuration parameters • 100% of the protocol, including: • all basic handshake features • incrementing, wrapping bursts of all size • all arbitration features • split and retry mechanisms • early burst termination • protected and locked transactions

  19. Example: AHB-OCP Bridge Verification OCP automatic creation AHB automatic creation Automatic Properties Scenarios AHB OCP Arbiter + Decoder Multithreading Master 1 DUT Entity 1 Master M Entity N Slave 1 AHB OCP Automatic Performance Properties Slave N

  20. Evolution of imPROVE-HDL • Capacity evolution (for identical solve-time) • Automatic and well adapted for OCP and AHB • Control-Oriented properties • Parallel protocols Formal Verification is a key technique for block-level verification 1M 300K 100K 40K 20K 2002 2003 2004 2001 2005

  21. Benefits for OCP-IP Organization • TransEDA is an active member of the OCP-IP FWG • Pro-active reviews the OCP specifications (comments, proposals) • Provides automatic validation of OCP-specific features with the powerful combination of a protocol implementation and a dedicated formal tool (imPROVE-HPK) • Donation of the OCP HPK libraries description

  22. Benefits for OCP-IP Members • A specification validated with a formal tool • Better quality and completeness • An automatic formal verification solution for OCP • For compliance and performance checking • Developed in relation with the OCP FWG • With active maintenance and support • Other tools for OCP dedicated support to come • VN-Cover for assertion coverage on OCP protocol • VN-Spec for OCP requirement management

  23. Summary • TransEDA owns a unique combination of formal, coverage and requirement tracking technologies • To provide its customers with a leading-edge coverage-driven verification solution • Automatic protocol verification is a corner stone of TransEDA offer • Relies on proven formal engines and extended assertion development expertise • TransEDA is committed to deliver best-in-class OCP-based designs verification tools • Available today: imPROVE-HPK OCP 1.0 & 2.0

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