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Permissible UFLS Time Delays

Understand the calculation of the rate of frequency decline in power systems and how generation deficit impacts system stability. Learn about the Maximum Permissible UFLS Time Delays to prevent unnecessary load shedding during frequency events.

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Permissible UFLS Time Delays

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  1. Permissible UFLS Time Delays UFLS SDT August 25-27, 2008 Meeting Presented by: Rob O’Keefe

  2. Calculated Rate of Hz Decline Rate of decline primarily a function of generation deficit and aggregate inertia  M dw/dt = Pgen – Pload (acceleration equation) [M is angular momentum, w is angular velocity]  M = GxH / 180xf (MW-sec**2 / degree), where G = MVA, f = 60 Hz * dw/dt = (Pgen – Pload) x 180x60 / (GxH) (degrees / sec**2)  dw/dt = (Pgen – Pload) x 180x60 / (GxHx360) (Hz / sec) * See Stevenson, eq. 14.7, p. 375.

  3. Calculated Rate of Hz Decline (cont.) dw/dt = (Pgen – Pload) x 180x60 / (GxHx360) (Hz / sec) [RFC MVA weighted average H = 3.96, round to 4.0]  dw/dt = (Pgen – Pload) x 7.5 / G (Hz / sec) Assuming 85 % PF…  dw/dt = (Pgen – Pload) x 6.375 / Pg (Hz / sec)  Example: 10 % generation deficit causes a .6375 Hz / sec rate

  4. Observed Rate of Hz Decline by Simulation Approximately .7 Hz / sec at 14 % generation deficit (.5 Hz / sec at 10 % deficit) Simulation also includes load and governing effects Rate = .05 x % deficit (Hz / sec)

  5. Series 1 – No UFLS, 14 percent generation deficit. Island frequency in Hz.

  6. Maximum Permissible UFLS Time Delays Goal is to prevent triggering more UFLS stages than necessary to remove the generation deficit or generation-load imbalance Therefore, when remaining generation-load imbalance is <= the UFLS program step size, time delay must not exceed time required for the next UFLS stage to trigger The shortest permissible delay is calculated when imbalance = step size x (# steps –1) This is because an initial imbalance larger than the UFLS program step size will cause a faster Hz / sec rate and will trigger next stages before previously triggered stages shed their load (which is okay until Hz approaches last stage) Delay should be set so last stage theoretically does not trigger in this case

  7. Example: 3 X 10% steps, 0.4 Hz increment between steps Answer = 36 cycles or .6 seconds total delay Initial imbalance = -20% (Rate = .05 x 20% = 1.0 Hz/sec) Time (seconds) Stage 1 trigger 0 Stage 1 dump .6 Stage 2 trigger .4 Stage 2 dump 1.0 Stage 3 trigger .4 + .2 (a) + .4 (b) = 1.0 (a) 1.0 Hz/sec x .2 sec = .2 Hz [from .4 to .6 seconds] (b) .50 Hz/sec x .4 sec = .2 Hz [from .6 to 1.0 seconds]

  8. Example: 3 X 10% steps, 0.3 Hz increment between steps Answer = 27 cycles or .45 seconds total delay Initial imbalance = -20% (Rate = .05 x 20% = 1.0 Hz/sec) Time (seconds) Stage 1 trigger 0 Stage 1 dump .45 Stage 2 trigger .3 Stage 2 dump .75 Stage 3 trigger .3 + .15 (a) + .30 (b) = .75 (a) 1.0 Hz/sec x .15 sec = .15 Hz [from .30 to .45 seconds] (b) .50 Hz/sec x .30 sec = .15 Hz [from .45 to .75 seconds]

  9. 3 Step UFLS Program Permissible Delay (sec) = ( Rate2 / Rate1 ) x ( 2 x Increment / Rate2 - Increment / Rate1) Rate1 = .05 Hz/sec x Step size (%) x 2 Rate2 = .05 Hz/sec x Step size (%) x 1 Increment = .3 Hz, Step size = 10%, Delay = 27 cycles (MAIN) Increment = .4 Hz, Step size = 10%, Delay = 36 cycles (MAAC)

  10. Example: 4 X 7% steps, 0.3 Hz increment between steps, delay = .57143 seconds or 34.3 cycles • Initial imbalance = -21% (Rate = .05 x 21% = 1.05 Hz/sec) • Time (seconds) • Stage 1 trigger 0 • Stage 1 dump .57143 • Stage 2 trigger .28572 • Stage 2 dump .85715 • Stage 3 trigger .28572 + .28572 (a) = .57143 • Stage 3 dump 1.14286 • Stage 4 trigger .57143 + .28572 (b) + .28572 (c) = 1.14286 • (a) 1.05 Hz/sec x .28572 sec = .30 Hz [from .28572 to .57143 seconds] • .70 Hz/sec x .28572 sec = .20 Hz [from .57143 to .85715 seconds] • .35 Hz/sec x .28572 sec = .10 Hz [from .85715 to 1.14286 seconds]

  11. 4 Step UFLS Program Permissible Delay = Rate2 x Rate3 / ( Rate2 x Rate3 – Rate1 x Rate3 + Rate1 x Rate2 ) x ( Increment / Rate1 - 2 x Increment / Rate2 + 3 x Increment / Rate3 – Increment x Rate2 / ( Rate1 x Rate3 ) ) Rate1 = .05 Hz/sec x Step size (%) x 3 Rate2 = .05 Hz/sec x Step size (%) x 2 Rate3 = .05 Hz/sec x Step size (%) x 1 Increment = .3 Hz, Step size = 7%, Delay = 34.3 cycles

  12. Example: 5 X 5% steps, 0.2 Hz increment between steps, delay = 29.46 cycles or .491 seconds • Initial imbalance = -20% (Rate = .05 x 20% = 1.0 Hz/sec) • Time (seconds) • Stage 1 trigger 0 • Stage 1 dump .491 • Stage 2 trigger .2 • Stage 2 dump .691 • Stage 3 trigger .4 • Stage 3 dump .891 • Stage 4 trigger .4 + .091 (a) + ,14533 (b) = .63633 • Stage 4 dump 1.12733 • Stage 5 trigger .63633 + .05467 (c) + .20 (d) + .23633 (e) = 1.12733 • (a) 1.0 Hz/sec x .091 sec = .091 Hz [from .4 to .491 seconds] • .75 Hz/sec x .14533 sec = .109 Hz [from .491 to .63633 seconds] • .75 Hz/sec x .05467 sec = .041 Hz [from .63633 to .691 seconds] • .50 Hz/sec x .20 sec = .10 Hz [from .691 to .891 seconds] • .25 Hz/sec x .23633 sec = .059 Hz [from .891 to 1.12733 seconds]

  13. Example: 5 X 6% steps, 0.2 Hz increment between steps, delay = 24.55 cycles or .4091 seconds • Initial imbalance = -24% (Rate = .05 x 24% = 1.2 Hz/sec) • Time (seconds) • Stage 1 trigger 0 • Stage 1 dump .4091 • Stage 2 trigger .16667 • Stage 2 dump .57576 • Stage 3 trigger .33333 • Stage 3 dump .74243 • Stage 4 trigger .33333 + .07577 (a) + .1212 (b) = .5303 • Stage 4 dump .9394 • Stage 5 trigger .5303 + .04546 (c) + .16667 (d) + .19697 (e) = .9394 • (a) 1.2 Hz/sec x .07577 sec = .09092 Hz [from .33333 to .4091 seconds] • .90 Hz/sec x .1212 sec = .10908 Hz [from .4091 to .5303 seconds] • .90 Hz/sec x .04546 sec = .04091 Hz [from .5303 to .57576 seconds] • .60 Hz/sec x .16667 sec = .10 Hz [from .57576 to .74243 seconds] • .30 Hz/sec x .19697 sec = .05909 Hz [from .74243 to .9394 seconds]

  14. 5 Step UFLS Program Permissible Delay = Rate2 x Rate4 / (Rate2 x Rate4 – Rate1 x Rate4 + Rate1 x Rate2) x ( 2 x Increment / Rate1 – 3 x Increment / Rate2 + 4 x Increment / Rate4 – Increment x ( Rate3 + Rate2) / ( Rate1 x Rate4 ) ) Rate1 = .05 Hz/sec x Step size (%) x 4 Rate2 = .05 Hz/sec x Step size (%) x 3 Rate3 = .05 Hz/sec x Step size (%) x 2 Rate4 = .05 Hz/sec x Step size (%) x 1 Increment = .2 Hz, Step size = 5%, Delay = 29.46 cycles (ECAR)

  15. Conclusion: • Permissible time delays specified under R2.6 are overly conservative and larger values (to within some percentage of the permissible delays in the examples given) should be acceptable • Could we… • Specify a variable permissible time delay in R2.6 using the formulas as a function of UFLS program # steps, step size and step increment with some margin applied, or • (2) Set a time delay value in R2.6 that is comfortably within the examples given for MAAC, ECAR and MAIN legacy UFLS programs?

  16. Of historical interest only…the following slide was a first attempt to determine UFLS time delays considering only generation deficits equal to the step size and time to trigger next stage It does not consider generation deficits larger than the step size

  17. UFLS Step Size

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