數位實習 LAB7

1. 數位實習 LAB7 1’s bit counter

2. 1’s bit counter A<8 bit> 1’s bit counter start <1 bit> reset <1 bit> clock <1 bit> done <1 bit> sum <4 bit>

3. Pseudo code sum = 0; while(A!=0) { if(A[0]) sum = sum+1; Right_shift A; }

4. Example

5. Example

6. Example

7. Example

8. Example

9. RTL

10. RTL

11. Algorithmic State Machine(ASM) • Graphic representation of FSM model • Equivalent to state-action table • Similar to a flowchart used for program description

12. ASM symbols

13. Reset ASM chart for 1’s bit counter S1 Load A B ← 0 0 0 1 s s 1 S3 S2 Done Shift right A 1 B ← B +1 A=0 ? 0 0 A[0] 1

14. Reset Control Unit Reset S1 Load A B ← 0 S1 0 LB LA 0 1 s s 0 0 1 1 s s S3 S2 1 Shift right A Done S2 S3 EA Done 1 B ← B +1 A=0 ? 0 1 EB z 0 A[0] 0 1 0 A[0] 1

15. Datapath A 0 log n n 2 w 0 Load LB Counter LA Load Enable EB Shift Enable EA Clock log n Data 2 n z B A[0]

16. RTL for 1’s bit counter A S reset clk 8 Control Unit Datapath LA EA LB EB z A[0] 2 4 8 a_reg sum done CurrentState

17. Simulation

18. Describe FSM reg state; case(state) 1'd0 : begin if(q==1) state=1'd1; else state=1’d0; end 1'd1 : begin state=1'd0; end default : begin state=1’d0; end endcase • Use “CASE” q=1 state0 state1

19. Describe FSM reg state; case(state) 1'd0 : begin if(q==1) state=1'd1; else state=1’d0; end 1'd1 : begin state=1'd0; end default : begin state=1’d0; end endcase • Use “CASE” q=1 state0 state1

20. Describe FSM reg state; case(state) 1'd0 : begin if(q==1) state=1'd1; else state=1’d0; end 1'd1 : begin state=1'd0; end default : begin state=1’d0; end endcase • Use “CASE” q=1 state0 state1

21. Shift (right) • case 1. for(i=1;i<n-1;i=i+1) A[i-1]=A[i]; A[n-1]=0; • case 2. A={0,A[n-1:1]}; • case 3. A=A>>1; (邏輯位移) A=A>>>1; (算術運算位移)

22. state Aacnt Clock done reset /start