An Affordable Solution That Bridges the Gap Between Firmware and RTL Implementations

1. Two for the Price of One An Affordable Solution That Bridges the Gap Between Firmware and RTL Implementations Alicia Strang, Robert C. Carden IV, Pei Suen Marvell Semiconductor, Inc. CA

2. Overview • Unified System Architecture for pre-silicon firmware development and rapid system integration • Simulation and Emulation Flow: RTL Verification andSystem Integration • Steps to Build This System • Result and Conclusions

3. System Architecture • Architecture for firmware development and rapid system integration. • Simulation test bench that can generate test scripts for FPGA environment • IP RTL integration into ARM SOCs • Firmware development (IROM) • FPGA environment to run test scripts generated by simulation

4. Test Code Unified System Architecture Diagnostic LED knob UART DDR SRAM JTAG/DAP ARM cortex XML seed RTL design IP 1 RTL design IP 2 … RTL design IP n System Architecture AHB/APB

5. Parallel System Phases (1) • Simulation Phase: Use Test IROM to test RTL and testbench • SoC system platform for simulation using modern constrained random and event driven verification methodologies • SystemVerilog code sends commands to the test IROM (embedded firmware) that executes on an ARM processor that is being simulated

6. Parallel System Phases (2) • Emulation Phase: Both Production and Test IROM • Replace the SystemVerilog code with a script that is executed on a PC that sends commands to the firmware running on an ARM processor within the FPGA environment. • Same PC program can execute these scripts against a board containing the actual chips.

7. Traditional flow Unified System Architecture developer’s platform flow Architecture Architecture RTL Design RTL Design RTL Verification RTL Verification Firmware Development System Integration Customer Integration Firmware Development System Integration Customer Integration Flow: RTL Verification and System Integration

8. Firmware Development • Using firmware driven tests brings true accuracy and performance to the front end of the design cycle. • Firmware is tested and debugged on RTL design IP before the design is fabricated. • Seamlessly run firmware with RTL models without sacrificing speed or accuracy.

9. Flow: RTL Verification and System Integrations Simulation Emulation (Board) Constrained Random Tests and reference model Tests Vectors and Golden Result Simulation Environment FPGA Chip Test EROM and Test IROM Custom EROM Production IROM Design IPs and Hardware RTL

10. Steps to Build This System • Generate firmware image from test firmware code • Synthesize firmware image together with RTL for FPGA and program FPGA PROM • Connect to PC host through serial port • Execute script to send commands through the serial port to the firmware • Process results from each command

11. Steps to Build This system (continued) • Run processor at FPGA speed (16 MHz) • Identify problems to be reproduced in simulation • Debug RTL and tweak firmware performance • Debug EROM written by customer • Execute script on post-silicon chip and process results

12. Debugging and Performance Analyse the Systems. Graphic presentation Waveform

13. Result and Conclusions • By using Unified System Architecture we reduced our wasted time and removed the need for separate system simulation and emulation testbenches. • This not only greatly reduces the amount of duplicated work but also bridges the critical gap between firmware and RTL implementations – two for the price of one.

14. Future Work • Add ability to generate random sequences of activities within the tests that are to be run on the FPGA • Add ability to run failed test in simulation once identified on FPGA