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Plan

A SystemC /TLM based design flow for embedded airborne electronic equipment development Pierre MOREAU Hardware Methodology & Certification - Airbus Operations S.A.S. Ludovic LETELLIER Hardware Methodology On behalf of Alyotech. Plan. Socket Process & Airbus application First Phase :

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Plan

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  1. A SystemC/TLM based design flow for embedded airborne electronic equipment developmentPierre MOREAUHardware Methodology & Certification - Airbus Operations S.A.S.Ludovic LETELLIERHardware Methodology On behalf of Alyotech

  2. Plan • Socket Process & Airbus application • First Phase : • Models Development • Platform Integration (Hw/Sw) • Second Phase : • ISS Open Source alternatives • Conclusion Workshop - November 2011

  3. Plan • Socket Process & Airbus application • First Phase : • Models Development • Platform Integration (Hw/Sw) • Second Phase : • ISS Open Source alternatives • Conclusion Workshop - November 2011

  4. SoCKET process • Formalism unification • Remove any semantics holes into HW/SW interface • Models transformation operators • Automation • Traceability • Overall coherency insurance • Tools interoperability • Keystone of 2 previous points Workshop - November 2011

  5. Socket Design Flow System requirements System Properties Global SoC spec. Metrics Metrics Trafficgenerators SoCArchitecture HLS Requirement traceability Platform assembly Header generation HW Properties SW Properties IP-XactSoC C/C++/ASM TLMLT Software Functionality Functional validation Instruction Set Simulator Software Functionality+timing TLMAT SW Performance validation Software RTL HLS Co-simulation/Co-emulation Software Silicon Deviceexecution Workshop - November 2011

  6. Socket Design Flow System requirements System Properties Global SoC spec. Metrics Metrics Trafficgenerators SoCArchitecture HLS Requirement traceability Platform assembly Header generation HW Properties SW Properties IP-XactSoC C/C++/ASM TLMLT Software Functionality Functional validation Instruction Set Simulator Software Functionality+timing TLMAT SW Performance validation Software RTL HLS Co-simulation/Co-emulation Software Silicon Deviceexecution Workshop - November 2011

  7. Main Topics • Architecture description (Coware, Magillem) • Components and platform description • Code generation (makefile, netlist, etc.) • SystemC/TLM LT virtual platform evaluation • Hardware requirement validation • Early software development • Functional safety • assertion based verification (PSL) • Monitors/checkers generation (ISIS) • Certification • Requirement traceability 1st Phase 2nd Phase Workshop - November 2011

  8. Plan • Socket Process & Airbus application • First Phase : • Models Development • Platform Integration (Hw/Sw) • Second Phase : • ISS Open Source alternatives • Conclusion Workshop - November 2011

  9. 1st Phase • Study Case specification • Coware tool experiment • SystemC TLM-PV models development • tsip, sgdma, timer, and uart modules • ARM Coware/Synopsys cpu model • Models and virtual platform validation with specific software • Application software development on virtual platform Workshop - November 2011

  10. 1st Phase • PlateformassemblywithCoware Workshop - November 2011

  11. 1st Phase • Simulation and results Workshop - November 2011

  12. 1st Phase • Hardware validation team feedback • Debug hardware behaviour with software tools • Halt and Resume • Freeze and Restore real time processing • 100% Visibility & Control • State machines • Variables • Buses • Tracing and logging • Golden Reference Platform • Consolidate platform evolution • Early validation of specifications Workshop - November 2011

  13. 1st Phase • Application software team feedback • Develop & Validate low level software sooner • Debug software with same tools than real platform • One time tool ramp-up • Debugging real world “utilities” (parsers, compilers, debugger scripts ...) • Mixed Hardware/Software Breakpoints • SW : instruction / data | HW : event / signal / bus data • Freeze & Restore real time execution • Get visibility not available on real SoC platform Workshop - November 2011

  14. 2nd Phase Motivation • End of Coware tool experiment • Need to find CPU Model • Need to find Bus Model • Need a way to rebuilt the platform • Need to implement traceability in SystemC models • Need to add monitors in the platform to increase safety IP-XACT in the design flow for embedded airborne electronic equipment development ABV in the avionicscontext: verification of safetyrequirements Workshop - November 2011

  15. Plan • Socket Process & Airbus application • First Phase : • Models Development • Platform Integration (Hw/Sw) • Second Phase : • ISS Open Source alternatives • Conclusion Workshop - November 2011

  16. 2nd Phase • Investigation for ARM Coware model replacement • ISS generator Trap-gen • TLM2 compatible bus model development • Magillem tool experiment • Components IP-XACT description • Platform Assembly • Code generation from IP-XACT files • NetlistSystemC • SystemC skeleton compatible with SCML2 Library • Makefile to compile platform • Traceability • Safety, SystemC monitors generation with ISIS Tool (TIMA) Workshop - November 2011

  17. 2nd Phase SystemCLTModel PSL properties SystemCSkeleton/Makefile/Netlist Magillem Packager ISIS Generator Template JET IP-XACT desc. Monitor/ Generator IP-XACT desc. MagillemGenerator Studio Magillem PLT Assembly MagillemRegisterView Generator Template JET IP-XACT desc. debugger Validation Fonctionnelle SW dev HAL Workshop - November 2011

  18. ISS alternative : Investigation • ISS needs : • Open source Licence • Moderate performance • OSCI TLM2 Sockets • Lowvirtualplatformintegration effort • Support GDB debugger • Active devellopement • Investigations : • QEMU • OVP • ORK1SIM • TRAP-GEN Workshop - November 2011

  19. ISS alternative : QEMU • http://wiki.qemu.org/Main_Page • From ST Webex : • Major breakthroughwith 0.13 • The libqemu.a no longer exists (not built, and API obsolete) • The License is not clear (GPL/LGPL) • Memory must be internal to QEMU (performance) • Wrapping in TLM needs modifications inside QEMU • Complex TLM platform not easy to connect to QEMU Workshop - November 2011

  20. ISS alternative : OVP • http://www.ovpworld.org/ • Open Virtual Platform • A lot of models : ARM, MIPS, PowerPC, SPARK • Support TLM2 sockets • Support GDB • Can boot linux • Open source models but simulator isonly free for non commercial use. Workshop - November 2011

  21. ISS alternative : Ork1sim • www.embecosm.com : • Application note : Building a Loosely Timed SoC Model with OSCI TLM 2.0: A Case Study Using an Open Source ISS and Linux 2.6 Kernel • Tutorial based on Or1ksim ISS http://opencores.org/openrisc,or1ksim • Implement TLM2 Sockets • Support GDB remote debugger • Support temporal decoupling • Can boot Linux • Memoriesinside ISS Workshop - November 2011

  22. ISS alternative : Trapgen • http://code.google.com/p/trap-gen/ • LGPL open source Licence • Generate multiple ISS from one architecture specification Workshop - November 2011

  23. ISS alternative : Trapgen • Generated ISS • OSCI TLM2 Sockets interface • Use SystemCscheduler • OS Emulator (system calls redirection) • Just in time compilation • Support interruptmodeling • Support GDB interface • Support multiprocessing • ISS examples : LEON 2/3, ARM 7/9, Microblaze • Drawbacks : • No cache or MMU models • Not a lot of feedback, but active development (LEON3) Workshop - November 2011

  24. ISS alternative : Trapgen • ARM9TDMI Model Selected • Source code modification needed • Interrupts IRQ ,FIQ port activation • CPU mode changing instruction bug • Register definition bug • Generated ISS Interrupt ports uses SystemC/TLM sockets • Need to modify timer, sgdmairq ports. • Custom ISS development possible with minimum effort Workshop - November 2011

  25. Plan • Socket Process & Airbus application • First Phase : • Models Development • Platform Integration (Hw/Sw) • Second Phase : • ISS Open Source alternatives • Conclusion Workshop - November 2011

  26. Global Results • Productivity gain • Early hardware architecture validation • Early software development • Easy platform duplication and distribution (executable file) • Complexity management • Better observability than real platform • HW/SW CoDebug • Safety and certification credit improvement (ex : fault injection) • Virtual Prototyping not Only for SoC technologies BUT also for Embedded Computer development • Data perenity • Use of standard : SystemC/TLM, IP-XACT, PSL • Potential bridges others languages, as SysML, SystemVerilog Workshop - November 2011

  27. Any Questions ? Workshop - November 2011

  28. SoCKET design flow System requirements System Properties Global SoC spec. Metrics Metrics SoCArchitecture Trafficgenerators HLS Requirement traceability HW Properties SW Properties Platform assembly Header generation IP-XactSoC C/C++/ASM TLMLT Software Functionality Functional validation Instruction Set Simulator TLMAT Functionality+timing Software SW Performance validation RTL HLS Software Co-simulation/Co-emulation Silicon Software Workshop - November 2011 Device execution

  29. SoCKET design flow System requirements System Properties Global SoC spec. Metrics Metrics SoCArchitecture Trafficgenerators HLS Requirement traceability HW Properties SW Properties Platform assembly Header generation IP-XactSoC C/C++/ASM TLMLT Functionality Software Functional validation Instruction Set Simulator TLMAT Functionality+timing Software SW Performance validation RTL Software HLS Co-simulation/Co-emulation Silicon Software Device execution Workshop - November 2011

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