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Chap 3.3~3.5 Construction an Arithmetic Logic Unit (ALU)

Chap 3.3~3.5 Construction an Arithmetic Logic Unit (ALU). Jen-Chang Liu, Spring 2006. Application ( programs ). Operating. Compiler. System (Windows , etc ). Software. Assembler. Instruction Set Architecture. Hardware. Processor. Memory. I/O system. Datapath & Control.

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Chap 3.3~3.5 Construction an Arithmetic Logic Unit (ALU)

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  1. Chap 3.3~3.5Construction an Arithmetic Logic Unit (ALU) Jen-Chang Liu, Spring 2006

  2. Application (programs) Operating Compiler System (Windows, etc) Software Assembler Instruction Set Architecture Hardware Processor Memory I/O system Datapath & Control Digital Design Circuit Design transistors What is“Computer Organization”? High level Low level

  3. Arithmetic Logic Unit (ALU)

  4. Outline in old textbook • Ch. 4.4: Simple ALU: logical op.s, add, sub Carry lookahead adder • Ch. 4.5: Multiplication • Ch. 4.6: Division

  5. ALU (Arithmetic Logic Unit) • The brawn of the computer • Functions • Arithmetic: add, sub • Logical: AND, OR, NOT… • MIPS uses 32-bit word, we need a 32-bit-wide ALU • 1-bit ALU • 32-bit ALU input 1 bit control signal 1-bit ALU output 1 bit input 1 bit

  6. Basic hardware building blocks Truth table: AND (MUX)

  7. 1-bit logical unit for AND, OR • 1-bit control signal to choose operation from MUX 1-bit ALU

  8. 1-bit Addition • Binary addition • Input/output for full adder

  9. 1-bit ALU: Addition (cont.) • Input/output truth table 3 inputs 2 outputs

  10. 1-bit ALU: Addition (cont.) • Truth table -> logical equation • Logical equation -> logical gates CarryOut = (b•CarryIn)+(a•CarryIn)+(a•b)+(a•b•CarryIn) AND OR t

  11. 1-bit ALU: AND, OR, ADD Data line Control line How do they look like in instructions?

  12. 32-bit ALU = 32 1-bit ALU (ripple carry adder)

  13. ALU: What about Sub (減) ? • For 2’s complement • 1-bit ALU for sub a-b = a+(-b) = a+b+1 complement: invert each bit of b

  14. Binvert 32-bit ALU with Sub Let this CarryIn be 1 when sub (ripple carry adder)

  15. What about other instructions? • Now,we have the following operations in ALU • and, or • add, sub • Other MIPS instructions: • slt: set on less than • beq, bne: branch on equality

  16. Implement slt • Recall • slt $t0,$s0,$s1 • $t0 = 1 if$s0<$s1 • Since $t0 is a 32-bit register 0 0 0……0 0 0 ? bit 1 31 0 2 Always 0 • if $s0 < $s1 • 0 otherwise • Check $s0<$s1 ? => $s0 - $s1 • Set output to 0 or 1

  17. How to compare using ALU? • Compare a and b (a-b) sign bit of (a-b) 1 a < b => (a-b) < 0 negative 0 a >= b => (a-b) >= 0 non-negative Set the result to 1 when sign bit is 1

  18. slt : 1th modification • For the 1-bit ALU We add a input signal for output

  19. slt: 2nd modification (1 bit) (2 bits) 31-th 1-bit ALU (sign bit) + Sign bit !!!

  20. Modification: • Less input • Set bit

  21. Implement beq, bne • Check for equality of two registers • a=b => (a-b) = 0 • Logical implementation: OR all output bits after sub Zero = (Result31+Result30+…+Result1+Result0) 所有bit為0, 設 Zero=1

  22. (1 bit) (2 bits) • Modification: • Zero output • Merge 1st CarryIn and BitInvert (Bnegate) • 兩者只有在減法時為1 ALU control line function 0 00 and 0 01 or 0 10 add 1 10 sub 1 11 slt

  23. Symbolic diagram for ALU operation function 0 00 and 0 01 or 0 10 add 1 10 sub 1 11 slt a b

  24. Outline • Simple ALU: logical op.s, add, sub • Multiplication • 3 versions of multiplication hardware • division

  25. Multiplication: startup example Multiplicand 1 0 0 0 Multiplier x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 Product 1 0 0 1 0 0 0 Multiplier 1 0 0 1 Multiplier 1 0 0 1 Multiplier 1 0 0 1 Multiplier 1 0 0 1 * Multiplication is done by iterative addition

  26. 1st version of mult. hardware Multiplicand 1 0 0 0 Multiplier x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 Product 1 0 0 1 0 0 0 • 32-bit multiplication • 32-bit x 32-bit = 64-bit LSB

  27. 1st version of mult. algorithm

  28. Drawbacks of 1st version • Half of the 64-bit of the multiplicand is always 0 • 64-bit ALU for 32-bit multiplication *why not shift the product right ? Multiplicand 1 0 0 0 Multiplier x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 Product 1 0 0 1 0 0 0 1 0 0 0 x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0

  29. 2nd version of mult. hardware 1 0 0 0 x 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 + 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0

  30. Drawbacks of 2nd version • The right 32-bit of the product is initially 0 • We take advantage that • Multiplier and product both shift right at each step

  31. 3rd version of mult. hardware multiplier 000…00000000

  32. Signed multiplication • The last algorithm will work for signed number, if • Right shifting of the product must preserve the sign !!! • Example: 11110001 11100011

  33. $t3 00011111111111111111111111111111 $t4 11000000000000000000000000000000 Multiplication in MIPS mult $t1, $t2 # t1 * t2 No destination register: Product could be 64 bits; need two special registers to hold it 3-step process $t1 01111111111111111111111111111111 X $t2 01000000000000000000000000000000 00011111111111111111111111111111 11000000000000000000000000000000 Hi Lo mfhi $t3 (move from Hi) mflo $t4

  34. Arithmetic Logic Unit (ALU)

  35. Outline • Simple ALU: logical op.s, add, sub • Multiplication • Division • 3 versions of division hardware

  36. Division: startup example Quotient Divisor 1000 1001010 Dividend 1 1 0 0 -1000 0010 0101 1010 -1000 10 Remainder • division => Iterative subtraction • Human judge whether subtract or not, how does • machine do it ?

  37. Simplified example • 4-bit division: 0111/0010 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 - 0 0 1 0 - 0 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 negative => 不減 => 還原被除數 negative => 不減 => 還原被除數 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 - 0 0 1 0 - 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 negative => 不減 => 還原被除數 positive => 可減 => 商數 1

  38. Simplified example (cont.) 0 0 0 0 0 0 1 1 - 0 0 1 0 0 0 0 0 0 0 0 1 餘數 positive => 可減 => 商數 11

  39. Divisor 000…00 00….0000 Dividend 1st version of div. hardware * Both operands are 32 bits 000…00 When to subtract?

  40. 可減 不可減，還原

  41. Drawbacks of 1st version • Half of the 64-bit of the dividend is always 0 • 64-bit ALU for 32-bit division

  42. 00….0000 Dividend 2nd version of div. hardware

  43. Remainder Q1Q2 000…000 Dividend Remainder Q 3rd version of div. hardware

  44. Example: 0111/0010

  45. Division in MIPS div $t1, $t2 # t1 / t2 Quotient stored in Lo Bonus prize: Remainder stored in Hi mflo $t3 #copy quotient to t3 mfhi $t4 #copy remainder to t4 3-step process

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