Introduction Part 1: Bits, bytes and a simple processor

1. IntroductionPart 1: Bits, bytes and a simple processor dr.ir. A.C. VerschuerenEindhoven University of TechnologySection of Digital Information Systems

2. M-1 Memory: 'word 0' ........... 2 1 0 'word 1' M 'bits' 'word 2' 'address space' '0' or '1' 'word N-1' 'word N' Basic processor - bits to memories • High-level program becomes 'machine code’ • Patterns of 1's and 0's (bits) stored in a memory... • Data structures are made suitable for hardware • Bit patterns stored in a memory! 'M' is power of 2: 4, 8 ('byte'), 16, 32 or 64 2m values in each word

3. Addressing a memory • The 'Central Processing Unit' (CPU) can access each memory word for reading or writing • To select which memory word is accessed,an 'address' must be given • Which consists itself out of a number of bits Addressable memory sizes are also a power of 2 !

4. Address sizes: how much memory ? • 'Standard' address sizes are: 16 bits: 65536 words 20 bits: > 106 words (1 'MegaWord') 24 bits: > 16106 words 32 bits: > 4109 words (4 'GigaWords') 64 bits: > 21019 words (unpronouncable) • Large, fast, reliable and easy-to-use memories are expensive must use large, slow, unreliable and difficult-to-use ones

5. 8 bits 16 bits must be kept intact! 16 bits 16 bits Memory addressing problems • Memory is generally addressed in 'bytes' (8 bits), while a word may contain more than one byte • Lowest bit(s) in address indicate the byte in a word • 'Partial write' and 'data misalignment' problems !

6. Instruction and data sizes • Instruction length may vary(in bytes or words) • When reading instruction,CPU must know at all times if more follows ! • Data size may vary(characters, integers, strings...) • Actual size must be encodedin instruction or data itself

7. Running a program: where are we ? • The Central Processing Unit must keep track of it's location in the program • It uses an 'Instruction Pointer' (IP) to do so • In general, the IP is incremented (IP  IP + 1) to point to the next instruction • The IP is also called 'Program Counter' (PC)

8. Modifying the ‘program flow’ • The IP should be loadable with a new value • Needed for IF..THEN..ELSE, CASE..OF, WHILE..DO, DO..UNTIL etcetera • Unconditional 'jumps' (load IP always) • Conditional 'jumps' (only load IP if test passes, IP  IP + 1 else) • Direct address (IP  N) • Relative address (IP  IP + N, N can be positive or negative) • Calculated address (IP  JumpTable[i], for instance)

9. Basic operations on data (1) • An 'Arithmetic and Logic Unit' (ALU) performs the actual data operations • Most operations use 2 input ('source') variables: 'Binary operations' • Arithmetic: Add, Subtract, Multiply, Divide • Logic: AND, OR, XOR • Comparing values is done with a subtract operation, discarding the result

10. Basic operations on data (2) • Compare may be in one instruction with conditional IP load • or set special 'flags' to indicate outcome (zero, carry) • or return special result word containing these flags • 'Unary operations' have only 1 source variable • Arithmetic: Negate, Increment (+1), Decrement (‑1) • Logic: NOT • Move data unmodified from source to 'destination'

11. ADD source ADD dest/srce1, srce2 'ACCU' ALU ALU ADD dest, srce1, srce2 ALU The number of addresses in an instruction • The maximum number of addresses stored in a single instruction classifies processors 2-address machine 1-address machine uses'accumulator’ as impliedsource/destination 3-addressmachine

12. Getting around the memory ‘bottleneck’ • Reading and writing the external memory takes a lot of time • Add a small memory (4..256 words) onto same chip as ALU: 'registers' • Can be made as fast as the ALU itself and allow multiple concurrent read and write operations • Can be used as multiple accumulators temporary storage for results

13. More on registers • Registers can be seen as small internal memory with short addresses • Allows powerful 3-address instructions on registers • May limit main memory accesses to data MOVE operations between registers and external memory The 'load/store' philosophy

14. CISC machine basics • Complex data structures require complex address calculations... • 'Complex Instruction Set Computers' (CISC’s) specifiy address calculations and actual ALU operation in a single instruction • Uses optimised separate hardware to calculate addresses • Needs few registers to store addresses • Packs a lot of information in one complex instruction

15. RISC machine basics • 'Reduced Instruction Set Computers' (RISC’s) use normal ALU operations to calculate addresses in a register for load/store moves • The ALU cannot be used for normal operations during address calculations • Needs extra registers to store calculated addresses • Requires several (simple) instructions where a CISC needs only one

16. Subroutines • A high-level subroutine/function call is done with the CALL instruction • Is a JUMP instruction which stores the location of the next instruction (the ‘return address’) • A single location does not allow nested subroutines • Fixed locations do not allow recursive subroutines • Using a Last-In-First-Out ('stack') memory to store return addresses removes these limitations

17. Getting out of subroutines again • The RET(urn) instruction loads the IP with the last stored return address • ...and 'pops the stack' • ...which uncovers the next-to-last return address working backwards in time !

18. Using the ‘stack’ to hold data • Also holds data during complex calculations • 'PUSH’ data onto the stack to store • 'POP' data from the stack to retrieve • Convenient:no need to know actual storage location, as long as PUSHes and POPs pair up correctly

19. D B C C C–D A A A+B A+B A+B A+B (A+B)x(C-D) (start) push A push B ADD push C push D SUB MUL pop result Basing a whole machine on the stack • By using the top- and next-of-stack storage locations for ALU operands, we can build a 'stack machine' Calculate (A+B)x(C–D) with a stack

20. Stack implementations • The actual stack can be implemented with special hardware on the CPU • Very fast (same speed as register set) • Severely limited in size (problematic for high-level programs) • The stack can also be stored in main memory

21. Stack implementation incompatibilities • Use a (special) register: the 'stack pointer' (SP) • Points to the current top-of-stack word OR • Points to the next free word on the stack • Growing down: PUSH/CALL decrements SP, POP/RET increments SP OR • Growing up: PUSH/CALL increments SP, POP/RET decrements SP • This gives a total of FOUR different and incompatible memory stack formats !

22. 'constants' instructions CPU 'constants' data instructions CPU 2) 'Harvard' architecture data 1) 'von Neumann' architecture constants CPU data instructions 3) 'Modified Harvard' architecture Memory interconnections • Different memory/processor interconnections exist, classifying computers further ‘von Neumann bottleneck’