PID meeting

1. PID meeting • SCATS : design status and simulation results • PIF : status design • Board design Christophe Beigbeder PID meeting

2. Young researcher project submitted by Nicolas on PID project. Christophe Beigbeder PID meeting

3. Electronics budget • Equipment • The main equipment resource requested by this ANR proposal is the funding to design the • FDIRC front-end electronics board – the mass production needed to instrument the whole SuperB • detector will be paid later by the collaboration. •  Front-end board: 5 k€ to produce three prototypes. So, assuming two iterations plus the final • pre-serial production, the total cost for this part is 15 k€. •  Chips • o Front-end: 10 k€ per multi-project wafer run (20 chips produced, among which 5 • encapsulated and 15 available as spares or for other tests) • o TDC: 25 k€ per multi-project wafer run (20 chips produced, among which 5 • encapsulated and 15 available as spares or for other tests) • Assuming as well three iterations for each chip (the last one being the pre-serial production), • the total cost for this part is 105 k€. •  Test setup: 10 k€ for its operation, maintenance and utilities. • The test stand will be located at LAL. Part of this equipment will be funded by the SuperB • LAL group and by the laboratory itself. That is why we only request 10 k€ for this part. • Summing up all the numbers above, the total cost for the whole FDIRC electronics prototype • chain is 130 k€. ANR money has to be spent on the submitted design Answer July 2011 Christophe Beigbeder PID meeting

4. Scats 500 KHz to 2 MHz evts/ch 20 MHz to 333 MHz Christophe Beigbeder PID meeting

5. SCATS Synopsis Design almost finished : Verilog and simulation in Actel FPGA done . Layout Done Layout Done Some problems with IC tools : mixed digital and analog simulation Layout in progress . Final assembling to be done . Generic Verilog to be target to IC tools libraries ( AMS) IO and interface has been crosscheck Christophe Beigbeder PID meeting

6. W0 W1 W7 En Fifo1 B<0> B<1> 16 Elementary memory cell B<15> 32 W0 W1 W7 En Fifo2 B<0> B<1> 16 B<15> AMS CMOS 0.35µm technology 1000µm 120µm Christophe Beigbeder PID meeting

7. FIFO_SCATS structure Scats 1 bit memory Scats 1 line 8 bits A.EL BERNI - LAL 7 Christophe Beigbeder PID meeting

8. Scats 16 lines 8 bits (named 16bx8w_fifo) Scats 32 lines (named 32bx8w_fifo) using two 16bx8w_fifo The Needed components for interfacing FIFO with Scats digital part have been added 8 Christophe Beigbeder PID meeting

9. Post layout simulations with parasitic extraction: Typical mean parameters: out_fifo1<0> rise time : 2.26 ns – maximum dispersion from memory cell to memory cell: 300ps Worse power parameters out_fifo1<0> rise time : 1.66 ns >>>>Match the requirements of a 40 MHz FIFO Worse time parameters: out_fifo1<0> rise time : 3 ns Christophe Beigbeder PID meeting

10. Board design Mezzanine : - CFD/ CFD like + Amp for charge measurement. - PIF chip in next version -> equips both PM test setup @ Orsay and CRT Mother board : ADC + Scats + FPGA - Associate time & charge - Data packing. - Bus interface : USB, GVbus -> equips both PM test setup @ Orsay and CRT Christophe Beigbeder PID meeting

11. Conclusion • SCATS will be submitted following the ANR decision ( July) • We start the design of the mezzanine board • Version with commercial components ( CFD/ CFD like) . • Version with PIF ( not before next year ) • We plan to design a mother board . • To receive the mezzanine • Used for the tests of SCATS • Compatible with the Bari’s / GV interface -> We all have to be careful to coordinate these activities and not do the same thing @ different places -> We all have to be careful to design a electronics which can fit the CRT requirements in terms of dimension and acquisition protocol Christophe Beigbeder PID meeting