1 / 50

DDR Evolution and Memory Market Trends

DDR Evolution and Memory Market Trends. Bill Gervasi Technology Analyst wmgervasi@attbi.com. Topics to Cover. The SDRAM Roadmap DDR-I & DDR-II Comparison Why DDR-I 400 is Boutique Memory Modules Changes. DRAM Evolution. DDR667. Mainstream Memories. 4300MB/s. 5400MB/s. DDR533.

berit
Download Presentation

DDR Evolution and Memory Market Trends

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DDR Evolution andMemory Market Trends Bill Gervasi Technology Analyst wmgervasi@attbi.com

  2. Topics to Cover • The SDRAM Roadmap • DDR-I & DDR-II Comparison • Why DDR-I 400 is Boutique • Memory Modules Changes

  3. DRAM Evolution DDR667 MainstreamMemories 4300MB/s 5400MB/s DDR533 3200MB/s DDR400 “DDR II” 2700MB/s DDR333 2100MB/s DDR400? 3200MB/s DDR266 1600MB/s DDR200 Simple,incrementalsteps 1100MB/s “DDR I” PC133 Is DDR-I 400 a temporary blip? “SDR”

  4. Key to System Evolution • Never over-design! • Implement just enough new features to achieve incremental improvements • Use low cost high volume infrastructure • Processes • Packages • Printed circuit boards

  5. Posed To Me at Platform & JEDEX Why will DDR-I at 400 MHz data rate be a “boutique” solution? Why will DDR-II at 400 MHz data rate be a “mainstream” solution? The answer is to look at what new is going into DDR-II

  6. From DDR-I to DDR-II LowerVoltage Prefetch 4 On-DieTermination DifferentialStrobe FBGAPackage CommandBus

  7. The DDR II Family • DDR II similarities to DDR I: • Compatible RAS/CAS command set & protocol • DDR II differences from DDR I: • DDR I = 2.5V, DDR II = 1.8V • Prefetch 4 • Differential data strobes • Improved command bus utilization: • Write latency as a function of read latency • Additive latency to help fill holes • New FBGA package & memory modules • Tighter package parasitics

  8. From DDR-I to DDR-II LowerVoltage LowerVoltage Prefetch 4 On-DieTermination DifferentialStrobe FBGAPackage CommandBus

  9. 1.8V Signaling 2.5V VDDQ 1.8V 1.60V VDDQ VIHac 1.43V 1.15V VIHdc 1.25V VIHac VREF 1.03V VILdc VIHdc 1.07V 0.90V VREF VILac VILdc 0.77V 0.90V VILac 0.65V VSS VSS 0V DDR-I(SSTL_2) DDR-II (SSTL_18)

  10. I/O Voltage Impact on Timing • Signal integrity is a serious challenge at high data rates!!! (duh!) • Assume 1mV/ps edge slew rate • DDR-I = 700 mV (VILVIH) = 700 ps • DDR-II = 500 mV (VILVIH) = 500 ps • Helps meet the need for speed

  11. 1.8V Signaling =Major Power Savings DDR533 @ 1.8V DDR266 @ 2.5V PC133 @ 3.3V

  12. From DDR-I to DDR-II LowerVoltage Prefetch 4 Prefetch 4 On-DieTermination DifferentialStrobe FBGAPackage CommandBus

  13. Prefetch • Today’s SDRAM architectures assume an inexpensive DRAM core timing • DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing core timing costs • DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O

  14. Prefetch 2 Versus 4 CK READ data Prefetch 2 Core access time Prefetch 4 Costs $$$ Essentially free

  15. Prefetch Impact on Cost By doubling the prefetch depth, cycle time for column reads & writes relaxed, improving DRAM yields DDR Family Pre-fetch Data Rate Cycle Time Starts to get REAL EXPENSIVE! 2 266 7.5 ns DDR-I 2 333 6 ns Comparable to DDR266 in cost 2 400 5 ns 4 400 10 ns DDR-II 4 533 7.5 ns 4 667 6 ns

  16. DDR-I 400 Prefetch • DDR-I prefetch of 2 means expensive core timing • Lower yields • Conclusion: DDR-I 400 will maintain a price premium for a long while

  17. Why Not Prefetch = 8? • DIMM width = 64 bits • PCs use 64b, servers use 128b (2 DIMMs) • 64 byte prefetch okay for PC, but… • 128 byte prefetch for servers wastes bandwidth • DDR-II must service all applications well to insure maximum volume  minimum cost

  18. From DDR-I to DDR-II LowerVoltage Prefetch 4 DifferentialStrobe On-DieTermination DifferentialStrobe FBGAPackage CommandBus

  19. Differential Data Strobe • Just as DDR added differential clock to SDR • DDR II adds differential data strobe to DDR I • Transition at the crosspoint of DQS and DQS • Route these signals as a differential pair • Common mode noise rejection • Matched flight times

  20. Differential Data Strobe VREF DQS DQShigh time DQSlow time Normal balanced signal VREF DQS DQShigh time DQSlow time Mismatched Rise & Fall signal Error!

  21. Differential Data Strobe DQS VREF DQS DQShigh time DQSlow time Normal balanced signal DQS VREF DQS DQShigh time DQSlow time Mismatched Rise & Fall signal Significantly reduced symmetry error

  22. From DDR-I to DDR-II LowerVoltage Prefetch 4 On-DieTermination DifferentialStrobe CommandBus FBGAPackage CommandBus

  23. Additive Latency • Command slot availability is disrupted by CAS latency even on seamless read bursts • Sometimes with odd CAS latencies, sometimes with even • These collisions can be avoided by shifting READs and WRITEs in the command stream • Additive latency shifts R & W commands earlier – applies to both

  24. Read Latency • In the past, data access from a READ command was simply CAS Latency • Combined with Additive Latency, ability to order commands better

  25. Read & Additive Latencies CK ACT RD data CAS Latency CK ACT RD RL = AL + CL data Additive Latency CAS Latency

  26. Write Latency • Complex controllers had collisions between command slots and data bus availability • These are eliminated in DDR II by setting Write Latency = Read Latency – 1 • Combined with Additive Latency, lots of flexibility in ordering commands

  27. Write & Additive Latencies CK ACT WR data Additive Latency = 0 WL = RL – 1 CK ACT WR WL = AL + CL – 1 = RL – 1 data Additive Latency CL – 1

  28. From DDR-I to DDR-II LowerVoltage Prefetch 4 On-DieTermination DifferentialStrobe FBGAPackage FBGAPackage CommandBus

  29. Managing Power(and its relationship to packaging)

  30. Power = CV2f%# Factors: • Capacitance (C) • Voltage (V) • Frequency (f) • Duty cycle (%) • Power states(# circuits in use) Keys to lowpower design: Reduce C and V Match f to demand Minimize duty cycle Utilize power states

  31. Package Capacitance (pF) TSOP-II Package Min Max Delta • Reduced capacitance lowers power, makes design easier Input Capacitance 2.0 3.0 0.25 Input/Output Capacitance 4.0 5.0 0.50 Approximate 10-25% reduction FBGA Package Input Capacitance 1.5 2.5 0.25 Input/Output Capacitance 3.5 4.5 0.50

  32. From DDR-I to DDR-II LowerVoltage Prefetch 4 On-DieTermination On-DieTermination DifferentialStrobe FBGAPackage CommandBus

  33. On-Die Termination Reduces system cost while improving signal integrity VTT =VDDQ ¸ 2 Data Controller DDR-I DRAM Data Controller DDR-II DRAM VDDQ ¸ 2 VDDQ ¸ 2

  34. DDR-I 400 Issues • DDR-I 400 systems are hard to design robustly • No vendor interoperability guarantees • DDR-II offers other performance benefits besides peak data rate • DDR-I 400 runs hot • Exists because DDR-II is late

  35. DDR-I 400 Conclusion • The JEDEC roadmap represents the industry focus for mainstream products • DDR-I tops out at 333 MHz data rate • DDR-II starts at 400 MHz data rate • This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume • It DOES mean that there will be price premiums for this speed bin

  36. Modules

  37. DDR-I Unbuffered DIMM Registered DIMM SO-DIMM Micro-DIMM New: 32b-DIMM DDR-II Unbuffered DIMM Registered DIMM SO-DIMM Micro-DIMM New: Mini-DIMM Modules

  38. Unbuffered & Registered DIMMs • Same physical size: 133 mm (5.25”) • New socket; more pins, tighter pitch • “Same plane referencing” pinout • Target markets unchanged • Servers • Workstations • Full form factor desktop PC

  39. SO-DIMM • Same size as before: 67.6 x 31.75 mm • Same 200 pin socket as before • Uses 1.8V key position • No longer supports x72 (ECC) or registered • Target markets change: • DDR-I: Mobile, blade server • DDR-II: Does not support blade server, small form factor PC possible

  40. Mini-DIMM • New to DDR-II… no DDR-I equivalent • Supports x72 (ECC) and registered • Larger than SO-DIMM: 82 mm • New socket required • Target market: blade server • Intent is to support stacking • If anyone figures out how to stack BGA

  41. Micro-DIMM • Same footprint: 45.5 x 30-ish mm • New connector • High pin count mezzanine connector • Two part: one on mobo, one on module • 0.4 mm pitch

  42. 32b-DIMM • New to DDR-I… no DDR-II version yet • X32 only • Ultra low cost • New connector • Target market: peripherals, e.g. printers

  43. What Can Change?

  44. Small Form Factor PC • PC memory usage flattened out • SO-DIMM or Mini-DIMM meet the needs of most PCs • DIMM could yield to smaller module for most desktop PCs • Saves ~10,000 mm2 board space

  45. FlexATX Footprint North Bridge Copper Slots With DIMM: 17k mm2 With SO-DIMM: 7k mm2 Area saved~ 60%

  46. Mobile • DDR-I SO-DIMM had 2X capacity of Micro-DIMM (assuming TSOP) • DDR-II Micro-DIMM has same capacity as SO-DIMM • Differences: • SO-DIMM supports 1st generation die • Micro-DIMM connector change scary • However, possible that the Micro-DIMM displaces the SO-DIMM for all mobile market

  47. Small Module Capacity

  48. Summary • DDR-II offers many incremental improvements over DDR-I • Lower voltage, higher prefetch, differential strobes, more efficient command bus, higher quality package, on-die termination • DDR-I 400 likely to stay a profitable niche • New module configurations may impact markets – watch for growth of Micro-DIMM, possible shrink of SO-DIMM in DDR-II generation

  49. Thank You

More Related