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Variations-Aware Circuit Designs for Microprocessors Marc Pons, Thesis Advisors: Francesc Moll, Jaume Abella. Electronic Engineering Department Universitat Politècnica de Catalunya. OUTLINE. Integrated Circuits Manufacturing The Need for Regularity Conclusion.
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Variations-Aware Circuit Designs for MicroprocessorsMarc Pons, Thesis Advisors: Francesc Moll, Jaume Abella Electronic Engineering Department Universitat Politècnica de Catalunya
OUTLINE Integrated Circuits Manufacturing The Need for Regularity Conclusion 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 2
IC MANUFACTURING [ASML] 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 3
LITHOGRAPHY LIMITS 10 -nce 1 um 0.1 [Intel] 2000 1990 2020 1980 2010 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 4
RESOLUTION ENHANCEMENT TECHNIQUES RETs are applied to mitigate process variations However RETs are computationally expensive for large circuits with arbitrary layout patterns
DECREASING YIELD [Synopsys] 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 6
INCREASING COSTS 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 7
DECREASING BENEFITS 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 8
DECREASING YIELD Regularity to Rescue [Synopsys] 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 9
REGULARITY TODAY TOMORROW [Rabaey] 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 10
LAYOUT LAYERS OUR PROPOSAL (REGULARITY) CONVENTIONAL (IRREGULARITY) 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 11
ADDER LAYOUTS 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 12
CONCLUSION Lithography Process Variations reduce Integrated Circuits Yield We propose to include Regularity in design to mitigate Process Variations We are studying the trade-offs involved
Thank you for your attention! 1st Barcelona Forum on Ph.D. Research in Electronic Engineering 14