Review:

1. Review: 22444 - Computer Architecture & Organization (1) Digital Logic

2. Digital Logic Review Objective Review a sample of MSI components and establish a standard drawing representation.

3. Digital Logic Review Logic Components • Small Scale Integration (SSI) AND, OR, NOT … • Medium Scale Integration (MSI) Multiplexer, Decoder, Register … • Large Scale Integration (LSI) Microprocessor, Memory … • Very Large Scale Integration (VLSI) Microprocessor, Memory …

4. Digital Logic Review Logic Circuits • Combinational Output depends on the current input. • Sequential Output depends on the current input and the previous output (history).

5. Digital Logic Review Logic Signals • Values • Totem–Pole (Binary): 0 or 1 • Tri–State: 0, 1, or high–impedance • Open–Collector: 0 or high–impedance • Inversion (bubble)

6. Digital Logic Review Logic Signals • Input • 0 or 1 • Output • 0 or 1

7. Digital Logic Review Logic Signals • Values • Totem–Pole (Binary): Never leave inputs “open-circuit” Never “short circuit” outputs • Tri–State: May connect multiple outputs but never enable more than one simultaneously • Open–Collector: May connect multiple outputs Inactive value ?

8. Digital Logic Review Logic Signals • Values • Totem–Pole (Binary): • Tri–State: • Open–Collector: Use pull-up resistor

9. M U X I0 I1 Y I2 I3 S1 S0 Digital Logic Review Signal Labels • MUX Active High Signal Active Low Signal

10. D E C O D E R Y0 Y1 Y2 E Y3 S1 S0 Digital Logic Review Signal Labels • Decoder

11. QA QB QC CLK S CLK S QA D Q ^ D Q ^ D Q ^ QB QC Digital Logic Review Timing Diagram • Clock Edge CLK S Next value Last value

12. LD CLK Digital Logic Review Registers • Group of “D” Flip – flops • Single “Clock” • Parallel “Load” R E G I S T E R D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

13. Digital Logic Review Registers • Parallel “Load” MUX 0 1 Q0 D Q Y D0 S MUX 0 1 Q1 D Q Y D1 S MUX 0 1 Q2 D Q Y D2 S MUX 0 1 Q3 D Q Y D3 S Load CLK

14. CLK Bus 2 3 Digital Logic Review Buses

15. Digital Logic Review End of Review