1 / 38

COE 202: Digital Logic Design Combinational Circuits Part 2

Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324. COE 202: Digital Logic Design Combinational Circuits Part 2. Objectives. Arithmetic Circuits Adder Subtractor Carry Look Ahead Adder BCD Adder Multiplier. Adder. Design an Adder for 1-bit numbers?. Adder.

bevis
Download Presentation

COE 202: Digital Logic Design Combinational Circuits Part 2

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Ahmad Almulhem, KFUPM 2009 COE 202: Digital Logic DesignCombinational CircuitsPart 2

  2. Ahmad Almulhem, KFUPM 2009 Objectives • Arithmetic Circuits • Adder • Subtractor • Carry Look Ahead Adder • BCD Adder • Multiplier

  3. Ahmad Almulhem, KFUPM 2009 Adder • Design an Adder for 1-bit numbers?

  4. Ahmad Almulhem, KFUPM 2009 Adder • Design an Adder for 1-bit numbers? • 1. Specification:2 inputs (X,Y)2 outputs (C,S)

  5. Ahmad Almulhem, KFUPM 2009 Adder • Design an Adder for 1-bit numbers? • 1. Specification:2 inputs (X,Y)2 outputs (C,S) • 2. Formulation:

  6. Ahmad Almulhem, KFUPM 2009 Adder • Design an Adder for 1-bit numbers? • 1. Specification: 3. Optimization/Circuit 2 inputs (X,Y)2 outputs (C,S) • 2. Formulation:

  7. Ahmad Almulhem, KFUPM 2009 Half Adder • This adder is called a Half Adder • Q: Why?

  8. Ahmad Almulhem, KFUPM 2009 Full Adder • A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry bit

  9. Ahmad Almulhem, KFUPM 2009 Full Adder • A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry bit

  10. Ahmad Almulhem, KFUPM 2009 Full Adder • A combinational circuit that adds 3 input bits to generate a Sum bit and a Carry bit Sum YZ X 00 01 11 10 S = X’Y’Z + X’YZ’ + XY’Z’ +XYZ = X  Y  Z 0 1 0 1 0 1 1 0 1 0 Carry YZ X 00 01 11 10 0 1 0 0 1 0 0 1 1 1 C = XY + YZ + XZ

  11. Ahmad Almulhem, KFUPM 2009 Full Adder = 2 Half Adders Manipulating the Equations: S = X  Y  Z C = XY + XZ + YZ

  12. Ahmad Almulhem, KFUPM 2009 Full Adder = 2 Half Adders Manipulating the Equations: S = ( X  Y )  Z C = XY + XZ + YZ = XY + XYZ + XY’Z + X’YZ + XYZ = XY( 1 + Z) + Z(XY’ + X’Y) = XY + Z(X  Y )

  13. Ahmad Almulhem, KFUPM 2009 Full Adder = 2 Half Adders Manipulating the Equations: S = ( X  Y )  Z C = XY + XZ + YZ = XY + Z(X  Y ) Think of Z as a carry in Src: Mano’s Book

  14. Ahmad Almulhem, KFUPM 2009 Bigger Adders • How to build an adder for n-bit numbers? • Example: 4-Bit Adder • Inputs ? • Outputs ? • What is the size of the truth table? • How many functions to optimize?

  15. Ahmad Almulhem, KFUPM 2009 Bigger Adders • How to build an adder for n-bit numbers? • Example: 4-Bit Adder • Inputs ? 9 inputs • Outputs ? 5 outputs • What is the size of the truth table? 512 rows! • How many functions to optimize? 5 functions

  16. Ahmad Almulhem, KFUPM 2009 Binary Parallel Adder • To add n-bit numbers: • Use n Full-Adders in parallel • The carries propagates as in addition by hand • Use Z in the circuit as a Cin • 1 0 0 0 • 0 1 0 1 • 0 1 1 0 • 1 0 1 1

  17. Ahmad Almulhem, KFUPM 2009 Binary Parallel Adder • To add n-bit numbers: • Use n Full-Adders in parallel • The carries propagates as in addition by hand Src: Mano’s Book This adder is called ripple carry adder

  18. Ahmad Almulhem, KFUPM 2009 Ripple Adder Delay • Assume gate delay = T • 8 T to compute the last carry • Total delay = 8 + 1 = 9T • 1 delay form first half adder • Delay = (2n+1)T Src: Course CD

  19. Ahmad Almulhem, KFUPM 2009 Subtraction (2’s Complement) • How to build a subtractor using 2’s complement?

  20. Ahmad Almulhem, KFUPM 2009 Subtraction (2’s Complement) • How to build a subtractor using 2’s complement? 1 Src: Mano’s Book S = A + ( -B)

  21. Ahmad Almulhem, KFUPM 2009 Adder/Subtractor • How to build a circuit that performs both addition and subtraction?

  22. Ahmad Almulhem, KFUPM 2009 Adder/Subtractor 0 : Add 1: subtract Src: Mano’s Book Using full adders and XOR we can build an Adder/Subtractor!

  23. Ahmad Almulhem, KFUPM 2009 Binary Parallel Adder (Again) • To add n-bit numbers: • Use n Full-Adders in parallel • The carries propagates as in addition by hand Src: Mano’s Book This adder is called ripple carry adder

  24. Ahmad Almulhem, KFUPM 2009 Ripple Adder Delay • Assume gate delay = T • 8 T to compute the last carry • Total delay = 8 + 1 = 9T • 1 delay form first half adder • Delay = (2n+1)T How to improve? Src: Course CD

  25. Carry Look Ahead Adder • How to reduce propagation delay of ripple carry adders? • Carry look ahead adder: All carries are computed as a function of C0 (independent of n !) • It works on the following standard principles: • A carry bit is generated when both input bits Ai and Bi are 1, or • When one of input bits is 1, and a carry in bit exists Cn Cn-1…….Ci……….C2C1C0 Carry bits An-1…….Ai……….A2A1A0 Bn-1…….Bi……….B2B1B0 Carry Out Sn Sn-1…….Si……….S2S1S0

  26. Carry Look Ahead Adder Ai Bi Pi Si Gi Ci Ci+1 Carry Generate Gi : Ci+1 = 1 when Gi = 1, regardless of the input carry Ci Carry Propagate Pi : Propagates Ci to Ci+1 Note: Pi and Gi depend only on Ai and Bi ! The internal signals are given by: Pi = Ai Bi Gi = Ai.Bi

  27. Carry Look Ahead Adder Ai Bi Pi Si Gi Ci Ci+1 The internal signals are given by: Pi = Ai Bi Gi = Ai.Bi The output signals are given by: Si = Pi Ci Ci+1 = Gi + PiCi

  28. Carry Look Ahead Adder Ai Bi • The carry outputs for various stages can be written as: C1 = Go + PoCo C2 = G1 + P1C1 = G1 + P1(Go + PoCo) = G1 + P1Go + P1PoCo C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 Pi Si Gi Ci Ci+1

  29. Carry Look Ahead Adder Conclusion: Each carry bit can be expressed in terms of the input carry Co, and not based on its preceding carry bit Each carry bit can be expressed as a SOP, and can be implemented using a two-level circuit, i.e. a gate delay of 2T

  30. Carry Look Ahead Adder C0 A0 B0 P0 G0 P1 P2 G2 G3 S0 Carry Look Ahead Block A1 B1 S1 C1 G1 A2 B2 C2 S2 C3 A3 B3 P3 S3 C4 C4

  31. Carry Look Ahead Adder Steps of operation: • All P and G signals are initially generated. Since both XOR and AND can be executed in parallel. Total delay = 1T • The Carry Look Ahead block will generate the four carry signals C4, C3, C2, C1. Total delay = 2T • The four XOR gates will generate the Sums. Total delay = 1T Total delay before the output can be seen = 4T Compared with the Ripple Adder delay of 9T, this is an improvement of more than 100% CLA adders are implemented as 4-bit modules, that can together be used for implementing larger circuits

  32. BCD Adder • BCD digits are valid for decimal numbers 0-9 • Addition of two BCD numbers will generate an output, that may be greater than 1001 (9). • In such cases, the BCD number 0110 is added to the result as a correction step • When adding two BCD numbers, the maximum result that can be obtained is: 9 + 9 = 18 If we include a carry in bit, then the maximum result that can be obtained is: 19 (10011) Both numbers 18 and 19 are invalid BCD digits. Therefore, a 6 needs to be added to bring them to correct BCD format.

  33. Adding two BCD numbers – Truth Table • The truth table defines the outputs when two BCD numbers are added • The function F is 1 for all invalid BCD digits, and therefore acts as a BCD verifier • To minimize the expression, a 5 variable can be used, or: • A 4 variable k map can be used to minimize the function F, and • The result is ORed with CO, since the function is always 1 whenever CO is 1 * From course CD

  34. Adding two BCD numbers – Minimization F Z1Z0 Z3Z2 00 01 11 10 00 01 11 10 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 F = Z3Z2 + Z3Z1 + CO

  35. Adding two BCD numbers – Circuit B3 B2B1B0 A3A2A1A0 4-bit Binary Adder Cout Carry In Z3 Z2 Z1 Z0 0 Correction Step 4-bit Binary Adder S3 S2 S1 S0

  36. Adding two BCD numbers - Steps • The two 4-bit BCD inputs are added by the 4-bit binary adder to produce the sum Z3Z2Z1Z0 and a Carry Out (Cout) • When Cout =0, the correction step executes by adding 0000 to Z3Z2Z1Z0, and the output remains the same • When Cout =1, the correction step adds 0110 to Z3Z2Z1Z0 to generate the corrected output • The output carry is the same as Cout • If additional decimal digits need to be added, the BCD adder can be cascaded, with the output carry of one phase connected to the input of the other

  37. Binary Multiplication • Similar to decimal multiplication • Multiplying 2 bits will generate a 1 if both bits are equal to 1, and will be 0 otherwise. Resembles an AND operation Multiplying two 2-bit numbers is done as follows: • B1 B0 • x A1 A0 • ---------------- • A0B1 A0B0 • A1B1 A1B0 + • ---------------------------------- • C3 C2 C1 C0 This operation is an addition, requires an ADDER

  38. Binary Multiplication • Therefore, for multiplying two 2-bit numbers, AND gates and ADDERS will be sufficient Half Adders

More Related