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LIRMM CNRS / University of Montpellier II FRANCE

Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. LIRMM CNRS / University of Montpellier II FRANCE. J. DALMASSO, M.L. FLOTTES , B. ROUZEYRE. Outline. Introduction and motivation Serialization vs compression ?

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LIRMM CNRS / University of Montpellier II FRANCE

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  1. Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains LIRMM CNRS / University of Montpellier II FRANCE J. DALMASSO, M.L. FLOTTES , B. ROUZEYRE

  2. Outline • Introduction and motivation • Serialization vs compression ? • Compression technique • Results • Conclusion

  3. Needs for Test Data Compression • Integration density  • Number of transistors  • Number of faults to test  • Test data volume  • Test time  => Multiple scan chains • ATE limits: • Memory depth • # ATE channels

  4. Issue N scan chains, M ATE channels, N > M How to fit M with N ? ATE M N CUT

  5. 1) Serialization of test data 1 Test slice 1 Pattern 1 test pattern = L test slices 1 test slice = divided into N/M slices of M bits in ATE • Short test sequences (No X's)

  6. 2) Horizontal (de)compression

  7. Test pattern compression          • Long test sequences (due to X's, low fill rate)

  8. Issues Given: M ATE channels, N scan chains, N > M • Fitting M with N ? • Serialization : short test sequences (No X's) • Compression : long test sequences (X's) • What is the best solution ?

  9. Proposed horizontal compression method • Features • Circuit netlist independent (suitable for IPs) • Test data independent (additional test patterns) • Specific tools independent • Low cost hardware decompressor • Input: test data sequence • actually applied to CUT • No impact on fault coverage • Take advantage of X's in test sequence

  10. Decompressor architecture From ATE M 0 0 0 0 Add Cells Output Shift Register N To scan chains

  11. Decompression principle Let Si = aN-1………………..…...…….a0 Let Si+1 = bN-1…………………..………b0 1/ it exists Sci = cM-1……c0/ Si+1 = Si + Sci c1 c0 0 0 0 0 aN-1…………………………………..…...…….a0

  12. dist Remark : P(cj: aibi) = 1/ 2dist => uniform distribution of inputs over adders Decompression principle Let Si = aN-1………………..…...…….a0 Let Si+1 = bN-1…………………..………b0 1/ it exists Sci = cM-1……c0/ Si+1 = Si + Sci c1 c0 0 0 0 0 bN-1…………………………………………..…b0 1 slice on N bits (Si+1) => 1 slice of M bits (Sci) in ATE

  13. Decompression principle Let Si = aN-1………………..…...…….a0 Let Si+1 = bN-1…………………..………b0 2/ it does not exist Sci = cM-1……c0 => serial loading of Si+1 b2M+1 bM+1 b1 b2M bM b0 A slice on N bits (Si+1) => N/M slices of M bits in ATE

  14. Compression • Case 1 : it exists Sci on M bits => 1 slice of M bits • Case 2 : it does not exist Sci => N/M slices of M bits • Compression • Maximize case 1 occurrences • Presence of X's • Columns ordering • X's assignment • Pattern ordering

  15. Compression algorithm: columns ordering P(cj: aibi) = 1/ 2dist ATE Channels ATE Channels Scan Chains Scan Chains

  16. while i< #Slices Compression algorithm: X's assignment I = 1 Si coded on N bits shift mode Initialization of Si i++ NO If SCi i++ YES add mode SCi assignment SCi coded on M bits Si+1 = Si + SCi END

  17. Initialization and assignment ATE Channels SC1: 0 1 0 Init => SC2: 0 1 0 SC3: 1 1 0 SC4: - - - Scan chains Init =>

  18. while i< #Slices Compression algorithm: X's assignment I = 1 Si coded on N bits shift mode Initialization of Si i++ NO If SCi i++ YES add mode SCi assignment SCi coded on M bits Si+1 = Si + SCi END

  19. a b c S1 1 0 1 0 0 1 0 0 0 ? S2 X X 1 X X 0 X 0 X S3 X 0 X X X 1 X X X S4 X 1 X X 0 0 0 X X S5 X X 0 1 X 0 1 X X Compressed Slice assignment S1 a b c 0 1 0 0 1 1 S2 S2 0 1 1 0 1 0 S3 S3 1 1 1 1 1 0 S4 S4 0 0 1 S5 S5

  20. Example SC1 : 0 1 1 Init => SC2 : 0 1 1 SC3 : 1 1 1 SC4 : 0 0 1

  21. V0 V1 V2 V3 V4 V1 V2 V4 V2 V4 V2 Pattern ordering • Pattern order has an influence on the number of compressed slices • Comparison of Pattern Ordering Algorithm: • Greedy algorithm • Simulated Annealing

  22. 1 1 0 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 1 1 1 0 X 0 1 1 0 1 0 1 1 1 X 0 0 0 1 0 1 1 1 0 0 0 X 1 X 1 1 1 0 1 X 1 X 0 1 0 1 0 1 X 1 X 0 X 0 0 0 1 0 X 1 1 X X 1 X 1 0 X X 0 0 X 1 X 0 X 0 0 X 1 0 X X X 1 1 0 X 1 X 1 X X 1 X X 0 X X 0 0 X 0 X X 0 0 X X X X 1 X 0 0 Decompression synchronization Original test Sequence Scan enable Control 0 0 S1 -> S2 : 0 1 S2 -> S3 : 1 1 S3 -> S4 : - - Compressed test Sequence Sc1 1 0 Sc2 0 0 FSM Sc3 0 1 CLK Sc4 1 1 Sc5 0 1 Sc6 1 0

  23. 1slice Compression vs serialization Serialization With Compression Test Time (loading) = Depth Data Volume

  24. Experiments: Compression vs Serialization • Test data sequences • Compression : X's needed • type 1 : no compaction • long test sequences (very low fill rate) • type 2 : compaction during ATPG • medium size test sequences • Serialization : No X's, • type 3 : all ATPG optimizations enabled (fault dropping, random filling, compaction …) • short test sequences (fully specified) • ATPG

  25. Experimental results S5378 circuit (214 flip-flops)

  26. Experimental results N= 32 scan chains , M = 8 ATE channels

  27. Comparison with Circular Scan [*] [*] B. Arslan, A. Orailoglu, "CircularScan: a scan architecture for test cost reduction", DATE'04, pp: 1290-1295.

  28. Post process for regular circuits (not for IPs):Fault simulation => Pattern Dropping • Pattern rejection algorithm Fully specified Test Sequence : T Test Sequence with X’s Compression & X’s Assignment P1: f1, f2 P1: f1, f2 P2: f3 P2: f3, f1, f2 T T* P* Pattern P Pattern With P* ≤ P

  29. Pattern Dropping Algorithm

  30. Conclusion • Simple horizontal compression technique • Circuit netlist independent (suitable for IPs) • Test data independent • Specific tool independent • Effective alternative to serialization • Compacted test sequences vs fully specified sequences

  31. Pattern Dropping Algorithm For i=1 to #Pi in T Add Pi to T* i++ Fault simulation of T* Number of detected faults: fdi i++ Remove Pi from T* NO If fdi > fdi-1 YES New test sequence T* End For

  32. Compression process summary Column Ordering Pattern Ordering Compression Pattern Dropping standard circuits only

  33. Perspectives • Other sequential decompressor structures • Co-optimization test architecture / compression test time: tam sizing / wrapper sizing / decompressor

  34. State Of The Art • At the CUT inputs (when test vectors are applied) • At the CUT outputs (when the test responses are checked)

  35. State of The ArtOutput Compression • Time compaction (MISR based solutions) • Risk of aliasing • Diagnosis difficult • Koenemann (IBM) ITC’01 • Spatial compaction (Xor trees based solutions) • Presence of unknown values • Mitra ITC’02 • Mixed methods e.g. Convolutional compactors • Rajski (MENTOR) ITC’04

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