LHC Upgrade R&D A. Seiden UCSC

1. LHC Upgrade R&D A. Seiden UCSC Trento, Italy February 13, 2006

2. LHC Upgrade During the past two years ATLAS and CMS have initiated an R&D program with the goal of being prepared to upgrade the detector for an order of magnitude increase in luminosity. The anticipated date for installation of the upgrades is around 2015, motivated by both the time when a large increase in luminosity will be required to significantly increase existing data samples per year of running and when aging effects will require replacement of some of the detector components. The upgrade will allow a 20 to 30% increase in mass reach for each experiment and the continuation of measurements on rare processes that are statistics limited after several years of data collection.

3. Inner Pixel Mid-Radius Short Strips Outer-Radius “SCT” Constraints

4. Large Number of Changes will have to be made to Inner Detector, little time for R&D My perspective will be from ATLAS, but many issues in common with CMS. ATLAS upgrade tracker plan: Inner Detector will be all silicon with several inner pixel layers, several short strip layers, and several longer strip layers. Pixels: (1) Innermost pixel detector has to be completely new concept due to charge trapping. A possible solution is to use 3-D detector modules. At larger radii will likely want 2 or 3 additional, more conventional, pixel layers. (2) Evolution of electronics will require development of pixel chip in smaller feature size CMOS. (3) Radiation hardness of all data transmission components not verified. Issue in common with strips.

5. Constraints SCT Barrel 3 Cables Ugly Beautiful

6. Large Number of Changes will have to be made to Inner Detector, little time for R&D Strips: (1) Organizational concept now is the single module (mechanically, electronically and for data transmission). A much larger copy of this won’t work, can’t scale-up services. Probably will need to develop a new structure – stave, requires significantly less cabling provided we can make related improvements. (2) The detectors presently used in the inner region (< 60 cm) would require too much voltage for efficient charge collection at the SLHC. Need for a new type of detector: for example n-on-p detector, which doesn’t need full depletion for successful operation. Not been used extensively in particle physics experiments. (3) New frontend needed, since present technology defunct. Require that it use significantly less power than present version to keep cooling and power cabling reasonable. A proposed solution SiGe BiCMOS. Potentially would use much less power than CMOS. (4) From point of view of safety and cable plant, need a different way of powering frontends. Possible solutions: DC-DC converters or serial powering. (5) Even if all the optical components are radiation hard, need a new multiplexing scheme to handle much more data and interface to stave. Solution: Will require changes in frontend and also a multiplexer receiver chip.

7. SLHC R=20cm SLHC R=8cm Charge Trapping in Silicon Efficiency of Charge Collection in 280 um thick p-type SSD G. Casse et al., (RD50): After 7.5 *1015 p/cm2, charge collected is > 6,500 e-

8. Short Strip Layers Will likely want 3 or 4 layers. At present most likely choice is n-on-p detectors in order to operate partially depleted and collect electrons. Resolution goal: σrφ=20 μm. For z, σz=0.5 mm (Present SCT) is achievable using stereo measurements. It has been suggested that perhaps localization to a given detector unit (3 cm) is adequate. This is an important question to be answered by tracking simulations. Area with 1% occupancy ≈ 3x10-2 cm2 (for example 100 μm x 3 cm). This should be acceptable as a detector element for tracking; will require a data transmission system that can deal with the rates.

9. Detectors Now have enough initial data to start modeling behavior of n-on-p short strip detector. Need to still understand annealing behavior, optimization of strip patterns, and cost tradeoffs (work with Mara Bruzzi and H. Sadrozinski).

10. Detectors Signal-to-Noise ratio S/N for p-type MCz SSD of 300 mm thickness as a function of operating temperature for three shaping times for short strips after a fluence of 2.2*1015 neq/cm2 and long strips after a fluence of 2.2*1014 neq/cm2 The maximum bias voltage is 600 V. The leakage current constant is set to ap = 2.5*10-17 A/cm. Noise RMS for p-type MCz SSD as a function of shaping time for short strips prerad, and after fluences of 2.2*1014 and 2.2*1015 neq/cm2 and long strips pre-rad and after a fluence of 2.2*1014 neq/cm2 . The maximum bias voltage is 600 V. The leakage current constant is set to ap = 2.5*10-17 A/cm.

11. Modules If we move to stave structures will have to develop two types: 1m long with short strips and 2m long with longer detectors would be ideal lengths for the two strip detector regions. Cost effective way to test ideas is to use CDF stave as a test bed. Almost ready to test. Purpose is to test low noise multi-module performance with ATLAS electronics. In coming year also provide test bed for power conversion schemes. Total length is 66 cm. Built around carbon/foam laminate with embedded cabling.

12. Modules • Fabricated in BeO • Fine pitch (100 micron) etched line-work • 7 micron Au thickness • Bond to pc card for test • Re-bond on stave • No connectors • Schematic similar to standard SCT hybrids • Electrically OK • 64 fabricated

13. Some Stave Issues A 1m stave with 3 cm long detectors will have 33 detectors linked together. This is a very large number and will require large numbers of hybrids. Would be good to use two levels of integration. The hybrid level, making larger module structures, and then linking a number of such module groupings together.

14. Possible Detector Unit

15. Short Strip Module Geometry For a given hybrid technology, only way to reduce ratio (hybrid mass)/(silicon mass) is to increase IC input density (suggestion of Maurice Garcia-Sciveres) Hybrid can neck down here to save mass Sensor is twice the strip length, With bond pads in the middle. IC hybrid sensor stave

16. Large Radius Important Issues: Cost, channel count, fitting cables through existing ATLAS. Likely will want 2 or 3 layers. Ideal detector size for a 6” wafer is about 9 cm x 9 cm. Desirable to use n – on – p detectors if chosen for short strips, but not mandatory. Important Issue: Do we need accurate z coordinate measurement or is localization to a given detector unit adequate? Depends on whether short strips provide accurate z information, probably need stereo measurements in one region or the other.

17. Module Level Integration (Supermodule) COOLING 9 cm 9 cm Units matched to 6 inch wafer to minimize costs. HYBRID 18 cm COOLING

18. 5 Year Upgrade R&D Plan R&D involves high-level conceptual and engineering design, followed by an extensive prototyping, testing and verification program for the individual components and finally the construction of a system prototype and the corresponding system test. The plan moves from individual components, which require radiation testing, to more highly integrated structures. Have about 3 years for the component R&D phase. Also want to make best use, in the case of the pixel B-layer, of the interface between the pixel R&D and the construction of a new B-layer. This layer could provide a good test of some of the Upgrade technology. New B-layer probably needed around 2012.