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A 110Mhz 350mW 0.6 m CMOS 16-State Generalized-Target Viterbi Detector for Disk Drive Read Channels. Srinath Sridharan Motorola L. Richard Carley Carnegie Mellon University. Outline. Motivation Background Implementation Architecture Circuits Results Conclusions. Motivation.
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A 110Mhz 350mW 0.6m CMOS 16-State Generalized-Target Viterbi Detector for Disk Drive Read Channels Srinath Sridharan Motorola L. Richard Carley Carnegie Mellon University
Outline • Motivation • Background • Implementation • Architecture • Circuits • Results • Conclusions
Motivation • Areal density 60% / year - 100% / year • Data rates 40% / year • Problems • Noise enhancement by front-end equalizer • Increased non-linearity in channel • Increasing amounts of ISI
Today’s Standard: PRML Systems • Equalize to PR polynomial + Viterbi Detector • Typical: PR4 = 0 0 0 1 0 -1 0 0 0 0 EPR4 = 0 0 0 1 1 -1 -1 0 0 0 • Pro • Reduces complexity of Viterbi detector (multiple by +/-1!) • Con • Equalizer enhances noise in matching PR target to channel • Linear target fails to capture non-linearity in system • Equalizer correlates noise in time degrades Viterbi error rate
Generalized Targets + Viterbi • Pro • Reduced SNR requirement for same error rate • Reduced noise enhancement by front end equalizer • Can adapt to non-linearities in channel • Con • Increased detector complexity • Increased difficulty for timing recovery
PRML vs Generalized Targets -1 10 For same symbol error rate SNR required 1-1.5 dB -2 10 -3 10 Probability of error PR4 -4 10 EPR4 -5 10 GEN-4 GEN-3 -6 10 22 23 24 25 26 26 27 28 29 30 31 32 SNR(dB)
Channel Parameters • PW50/T 3.16 • Write gap 0.287mm • MR read gap 0.25mm • Medium Hc 2600 Oe • Medium MrT 0.6 memu/cm2 • Velocity 544.2 inches/sec • Code 8/9(0,4/4) RLL Reference : Nick Zayed, L.R. Carley, “ Equalization and Detection for Nonlinear Recording Channels with Correlated Noise”, INTERMAG May 1999
2 1 1 1 2.12 1.40 1.42 What is the difference? EPR4 target : Integer coefficients Generalized target : Any coefficient
Delay LMS :Equalizer Coefficients LMS Error signal Update EQ coeffs m1 Fixed target e.g: PR4, EPR4 Input signal FIR Equalizer Viterbi Detector Noiseless target
en LMS m1 m2 x In FIR Equalizer Viterbi Detector Delay NT(s) Generalized targets? • LMS on Equalizer and targets simultaneously • Convergence over parabolic surface
6 5 Less noise enhancement by front end Lower probability of error 4-5 X reduction Using PR targets 4 3 Magnitude 2 Using Generalized targets 1 0 0 1 2 3 Frequency rads/sec Frequency response of equalizer after training System Performance Improvements
Detector Architecture 6 32 branch values Branch metric Unit 6 Digital input 5 5 ACS units 16 ACS Decisions 1 Clock 1 Path Trace-back - 16 stages 1 Binary Decision Output 1
Branch-Metric Unit Noiseless targets NT(31) NT(1) NT(0) I I Input, I BM(31) BM(1) BM(0) Branch metrics
Branch Metric Unit (cont.) NT NT |NT-I| I Input, I > M 1 0 BM Compute square Saturated value, S M and S : Decided by precision needed in BM For BM : 7 bits precision M = 11 S = 121 1 0 BM
Add-Compare-Select Unit p1 b1 p2 b2 10 5 p2 b2 sum2 sum 1 p1 b1 10 5 10 b1 5 p1 pfinal 10 10 b2 Evaluate p1+b1 - b2- p2 p2 decision 1 0 pfinal = min(p1+b1 , p2+b2) 10 Updated path metric
Decisions from ACS unit Stage 1 latches muxes Stage 2 4 state Viterbi Trace-Back Unit
3 mm 3 mm Die Photograph
Results Component Power @ Delay Die Area 2 125MHz ( mW) ( ns) (mm ) Branch 158 5 0.9 Metric Unit Viterbi ACS 136 8 1.21 (Array of 16) Viterbi 47 1.2 0.34 Trace-Back TOTAL 350 mW 8 ns 2.92 (w/clock power) (limit) Experimental 386 mW 9 ns 2.92 Measurements (limit) (scaled from 110Mhz)
Technology Scaling Effects • Speed • proportional toa • ais inversely proportional to minimum feature size • Power • proportional to 1/a2 • Area • proportional to 1/ a2 • ISI handling capacity for the same die area • 6 to 7 symbols in 0.35mand 0.25mCMOS processes
Conclusions • A 16-State Viterbi detector capable of accepting any linear / non-linear noiseless target • Generalized targets • lesser noise enhancement by front end equalizer • lower probability of error • Scaling CMOS feature sizes • increased ISI span (6-7 symbols) • Proceed towards true MLSD