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Beam Secondary Shower Acquisition System: The TWEPP14 experience. Jose Luis Sirvent Blasco PhD. Student. STUDENT MEETING 29/09/2014. 1.Introduction 1.1 General Info. Held in Aix-en-Provence 22-26 September Main topics: Electronics for HEP Readout ASICS Pixel detectors
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Beam Secondary Shower Acquisition System: The TWEPP14 experience Jose Luis SirventBlasco PhD. Student STUDENT MEETING 29/09/2014 BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch)
1.Introduction1.1 General Info BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) • Held in Aix-en-Provence • 22-26 September • Main topics: • Electronics for HEP • Readout ASICS • Pixel detectors • Optical links • Beam instrumentation • …. • 173 Abstracts presented • 93 Posters • 43 Parallel presentations
1.Introduction1.2 The Family picture Me! A Very young researcher BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch)
2. The talks2.1 Highlights of the 46 presented BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) • HEP Electronics in France(C.P. Colledani) • IN2P3 presentation and Readout ASICS introduction. Colaborations and Structure • From Deep Sea to Deep Space with the ANTARES and KM3NeT Undersea Neutrino telescopes (V. Bertin) • ITER, DEMO: On the road to Sustainable Fusion Energy (J.M. Ane) • Very nice presentation about Fusion Energy, history, general concepts and ITER project status. • TDCPix: Tracking fot the NA62 GigaTracker(M.Noy) • Hybrid Pixel detector readout ASIC for the NA62 GigaTracker detector. 1800 pixels 300x300um • Transmission with no need of trigger trough continuous data stream with 4x 3.2 Gb/s Serializers • The CMS Central Hadron Calorimeter DAQ System Upgrade (A. Whitbeck) • Plans, status and schedule. QIE10 board presented, front-end overview. • Atlas Tile Calorimeter Electronics and Future Upgrades (G.Usai) • Nice overview of the upgrade plans with their 3 different FE options FATALIC / QIE10 / 3in1 • First Irradiation Test of the RCU2 (C.Zhao) • They are using SmartFussion2 for their board with Serializers, board tested under radiation • SEL, SEU ,PLL, TID Functional up to 10’s Krad but reprogramming failed after 2.5Krad • PLL stability is a concern, lock loss, SEL shown corrected on next bach of devices (also for Igloo2) • Design and performance of dedicated Very Front End for SiPM: From Spiroc to Triroc (L. Raux) • Omega In2P3 presentation showing their readout asics, some of them where considerer for our system • Low noise 4-Channel Front End asic with on-chip DLL for the Upgrade of the LHCb calorimeter (E. Picatoste) • ICECAL V3 presentation and performance testings: Input impedance ~50 +- 5 ohms // Linearity >> 1% • FEAST2: a Production Grade 10W Radiation Tolerant DC/DC Converter (F. Faccio) • DC/DC Mocule availability and analysis, great speaker! • Versatile Transceiver and Transmitter Production for Phase I Upgrades of LHC Experiments (J.Troska)
3.The coffee breaks: 3.1And the unofficial research meetings around a beer BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) • E. Picatoste & D.Gascon(UB, working on ICECAL) • ICECAL V3 under study Possible availability for us (includes 4 channels, mux & ADC Driver) • Developing now test board • Andrew Whitbeck(FERMILAB, working with QIE10/11) • Confirmation of QIE10p6 & QIE11 release for SIPM (main difference QIE10/11 Pulse polarity) • Stephen Groadhouse(U. Virginia, working with T.Grassi on ngCCM) • Detailed talk about the ngCCM board routing and pourpose (this is the motherboard of Igloo2 Mezzanine) • Jose Carlos Rasteiro Da Silva (CERN, working on the routing of Igloo2 Mezzanine) • Discussion about Mezzanine status and routing advices, the board is about to be fabricated • Will be on the organization comitee for TWEPP15 on Lisbon. • Manoel Barros Martin (CERN, working on GBT-FPGA soon on BI) • He’ll work with the VFC board firmware on Arria X (GBT code similar to Cyclone V) • Advices for GBT implementation on Igloo2 for compilation stability • Sophie Baron (CERN, working on GBT-FPGA / GBTx …) • Suggestions about getting GBTx samples and confirmation of GBTx SAT board development • We’ll be on touch for GBTx board development for Igloo2 Substitution. • Pedro Miguel Vicente Leitao(CERN, working on GBTx & ePLL) • Nice talk about the GBTx E-Links and direct connectivity with FE ASICs
4.Poster Sessions4.1 Some highlights from the 93 presented BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) • The eCDR-PLL IC, a Radiation Tolerant ASIC for Clock and Data Recovery and Deterministic Phase Clock Synthesis (P. Vicente Leitao) • CDR for TTC decoders and jitter cleaner in radiation environment (E.g. Igloo2 FPGAs) • Clock synthesis for BE & FE applications. • High Reliability DC/DC Converter module for Electronic Boards Equipped with FPGAs (W. Vigano) • DC Converter for VCF board • The CMS Hadron Calorimeter Detector Control System Upgrade (O. Sahin) • Replacement VME uTCA and the use of GLIB board for GBT link (Communication with ngCCM and QIE boards) • A New Generation of Charge Integrating ADC (QIE) for the CMS HCAL Upgrade (J. Hirschauer / A.Whitbeck) • Official presentation of QIE1, and summary of QIE10 performance • A software package for the full GBT chipset LifeCycle(S. Feger) • Easy configuration of 300 GBTx registers, powerful software for GBT link status visualization. • The GBT-SCA, a Radiation Tolerant ASIC for Detector Control and Monitoring Applications in HEP Experiments (A. Caratelli) • Presentation of GBT-SCA for slow control, status and availability (Q1 2015?) • CLIC-ACM: Generic Modular Rad-Hard Data Acquisition System Based on CERN GBT Versatile Link (S. Magnoli) • System similar to ours, being the GBTx the core of the system. • DDL, the ALICE Data Transmission Protocol and its Evolution from 2 to 6 Gb/s (F.Costa) • Test Bench Development for the Radiation Hard GBTX ASIC (P.VicenteLeitao) • GBTx ASIC tested with X-rays up to TID 100MRad and still functional < 10% total jitter increase. • SEU data presented as well (no Config Errors observed below 12.9 MeV/mg/cm2). Burst of wrong frames • Secondary Particle Acquisition System for the CERN Beam Wire Scanners upgrade (J.L.Sirvent) • You know well what I do (I hope..) • The CMS HCAL FEE Control Module (S. Goadhouse) • ngCCM module, architecture, functionality and conectivity with Igloop2 UMd mezzanine board • The GBT-FPGA Core: Features and Challenges (M.Barros)
5. Proceedings Submission5.1 And my following planes Next steps: 1. Write 2nd CERN’s Progress Report 2. Check Igloo2 UMd Mezzanine final schematics & routing. 3. Prepare Slides for BI-Day 26-Oct. 4. Small modifications on QIE10 Board before submission on PCB-Pool 5. Check ICECAL V3 availability and plans for board. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch)