Lab 5: FSM and BCD counters

1. Lab 5: FSM and BCD counters • Implement the vending machine of lab 2 • A two-digit BCD counter • two BCD counters • can load data in parallel

2. Vending Machine module machine (ti,fi,out,state,rst); output out; output [1:0] state; input ti,fi; input rst; reg [1:0] state ,nextstate; reg t1,t2,f1,f2;

3. BUFG g1 (.O(clk_hi), .I(clki)) ; BUFG g2 (.O(clk), .I(clk_sl)) ; always @ (posedge clk_hi) cnt = cnt +1 ; assign clk_sl = (cnt >= 15’h4000) ; assign out = (state == 3); always @ (posedge clk) begin t2 = t1 ; t1 = ti ; f2 = f1 ; f1 = fi ; end assign t = t1 & ~t2 ; assign f = f1 & ~f2 ; Vending Machine

4. always@(t or f ) case(state) 0: begin if (f) nextstate = 1; else if (t) nextstate = 2; else nextstate =0; end 1: begin if (f) nextstate = 2; else if (t) nextstate = 3; else nextstate =1; end Vending Machine

5. 2: begin if(f) nextstate = 3; else if(t) nextstate = 3; else nextstate =2; end 3: nextstate = 0; endcase endmodule Vending Machine

6. Global Clock Buffers • Clock Buffers are low-skew, high drive buffers • Also known as Global Buffers • Drive low-skew, high-speed long line resources • Drive all Flip-Flops and Latches in FPGA • Can also be used for high-fanout signals • Instantiation: if the BUFG component is instantiated, software will select one of these buffers based on the design • BUFG u1 (.I(clki),.O(clk)) ;

7. IOBs Organized As Independent Banks • As many as eight banks on a device • Package dependent • Each bank can be assigned any of the 16 signal standards • XC2S50 PQ208 • GCK 0: pin 80 • GCK 1: pin 77 • GCK 2: pin 182 • GCK 3: pin 185

8. 4-bit binary counter w/ parallel load

9. count load' load c_en c_en A0 async

11. Generate any count sequence: • E.g.: BCD counter  Counter w/ parallel load

12. Counting Modulo 7: Detect 7 and Asynchronously Clear • A synchronous 4-bit binary counterwith an asynchronous Clear isused to make a Modulo7 counter. • Use the Clear feature todetect the count 7 andclear the count to 0. Thisgives a count of 0, 1, 2, 3, 4,5, 6, 7(short)0, 1, 2, 3, 4, 5,6, 7(short)0, etc. • DON’T DO THIS! Referred to as a “suicide” counter! (Count “7” is “killed,” but the designer’s job may be dead as well!) Q3 D3 Q2 D2 Q1 D1 Q0 D0 Clock CP 0 LOAD CLEAR

13. 0 Q3 D3 0 Q2 D2 0 Q1 D1 0 Q0 D0 Clock CP LOAD Reset CLEAR Counting Modulo 7: Synchronously Load on Terminal Count of 6 • A synchronous 4-bit binarycounter with a synchronousload and an asynchronousclear is used to make a Modulo 7 counter • Use the Load feature todetect the count "6" andload in "zero". This givesa count of 0, 1, 2, 3, 4, 5, 6,0, 1, 2, 3, 4, 5, 6, 0, ... • Using don’t cares for statesabove 0110, detection of 6 can be done with Load = Q4 Q2

14. Counting Modulo 6: Synchronously Preset 9 on Reset and Load 9 on Terminal Count 14 • A synchronous, 4-bit binarycounter with a synchronousLoad is to be used to make aModulo 6 counter. • Use the Load feature topreset the count to 9 onReset and detection ofcount 14. • This gives a count of 9, 10, 11, 12, 13, 14, 9, 10, 11, 12, 13, 14, 9, … • If the terminal count is 15 detection is usually built in as Carry Out (CO) 1 Q3 D3 0 Q2 D2 0 Q1 D1 1 Q0 D0 Clock CP Reset LOAD CLEAR 1

15. BCD Counter • Function table • TC = 1, if Q== 9; otherwise, TC = 0

16. A two-digit BCD counter • two synchronous BCD counters • two 7-segment decoders